A Digital Phase-Locked Loop With Background Supply Noise Cancellation. - Yen-Min Tseng; Yu-Chi Yen; Shen-Iuan Liu (VLSI-DAT, 2021)

An Adaptive Digital PLL Based on BBPFD Transition Probability. - Zhi-Heng Kang; Yu-Chi Yen; Guan-Yu Su; Shen-Iuan Liu (VLSI-DAT, 2022)

An Injection-Locked Clock Multiplier With Injection Strength Calibration. - Yen-Min Tseng; Yu-Chi Yen; Shen-Iuan Liu (VLSI-DAT, 2022)

A 59.6fsrms Jitter Sub-Sampling PLL With Foreground Open-Loop Gain Calibration. - Yu-Chi Yen; Shen-Iuan Liu (IEEE Trans. Circuits Syst. II Express Briefs, 2025)