LASER: layout-aware analog synthesis environment on laker. - Yu-Ching Liao; Yen-Lung Chen; Xian-Ting Cai; Chien-Nan Jimmy Liu; Tai-Chen Chen (ACM Great Lakes Symposium on VLSI, 2013)

A layout-aware automatic sizing approach for retargeting analog integrated circuits. - Yen-Lung Chen; Yi-Ching Ding; Yu-Ching Liao; Hsin-Ju Chang; Chien-Nan Jimmy Liu (VLSI-DAT, 2013)

Multiple Silicon Nanowires with Enzymatic Modification for Measuring Glucose Concentration. - Cheng-Chih Hsu; Yu-Ching Liao; Yen-Ting Tsai; Hsin-I Yeh; Chyan-Chyi Wu (Micromachines, 2015)

Physics-Based Models for Magneto-Electric Spin-Orbit Logic Circuits. - Hai Li 008; Dmitri E. Nikonov; Chia-Ching Lin; Kerem Yunus Çamsari; Yu-Ching Liao; Chia-Sheng Hsu; Azad Naeemi; Ian A. Young (CoRR, 2021)

Performance Benchmarking of Spin-Orbit Torque Magnetic RAM (SOT-MRAM) for Deep Neural Network (DNN) Accelerators. - Yandong Luo; Piyush Kumar; Yu-Ching Liao; William Hwang; Fen Xue; Wilman Tsai; Shan X. Wang; Azad Naeemi; Shimeng Yu (IMW, 2022)

Chat-log Disentanglement via Same-Thread Classification and Direct-Reply Prediction. - Chia-Hui Chang; ZhiXian Liu; Thamolwan Poopradubsil; Yu-Ching Liao; Yu-Hao Wu (PACLIC, 2022)

Event Source Page Discovery via Policy-Based RL with Multi-task Neural Sequence Model. - Chia-Hui Chang; Yu-Ching Liao; Ting Yeh (WISE, 2022)