Entropy-Assisted Multi-Modal Emotion Recognition Framework Based on Physiological Signals. - Kuan Tung; Po-Kang Liu; Yu-Chuan Chuang; Sheng-Hui Wang; An-Yeu Wu (CoRR, 2018)

AdaBoost-assisted Extreme Learning Machine for Efficient Online Sequential Classification. - Yi-Ta Chen; Yu-Chuan Chuang; An-Yeu Andy Wu (SiPS, 2019)

Online Extreme Learning Machine Design for the Application of Federated Learning. - Yi-Ta Chen; Yu-Chuan Chuang; An-Yeu Andy Wu (AICAS, 2020)

Task-Projected Hyperdimensional Computing for Multi-task Learning. - Cheng-Yang Chang; Yu-Chuan Chuang; An-Yeu Andy Wu (AIAI (1), 2020)

IP-HDC: Information-Preserved Hyperdimensional Computing for Multi-Task Learning. - Cheng-Yang Chang; Yu-Chuan Chuang; An-Yeu Andy Wu (SiPS, 2020)

Dynamic Hyperdimensional Computing for Improving Accuracy-Energy Efficiency Trade-Offs. - Yu-Chuan Chuang; Cheng-Yang Chang; An-Yeu Andy Wu (SiPS, 2020)

FL-HDC: Hyperdimensional Computing Design for the Application of Federated Learning. - Cheng-Yen Hsieh; Yu-Chuan Chuang; An-Yeu Andy Wu (AICAS, 2021)

Hyperdimensional Computing with Learnable Projection for User Adaptation Framework. - Yu-Ren Hsiao; Yu-Chuan Chuang; Cheng-Yang Chang; An-Yeu Andy Wu (AIAI, 2021)

PQ-HDC: Projection-Based Quantization Scheme for Flexible and Efficient Hyperdimensional Computing. - Chi-Tse Huang; Cheng-Yang Chang; Yu-Chuan Chuang; An-Yeu Andy Wu (AIAI, 2021)

An Arbitrarily Reconfigurable Extreme Learning Machine Inference Engine for Robust ECG Anomaly Detection. - Yu-Chuan Chuang; Yi-Ta Chen; Huai-Ting Li; An-Yeu Andy Wu (IEEE Open J. Circuits Syst., 2021)

MulTa-HDC: A Multi-Task Learning Framework For Hyperdimensional Computing. - Cheng-Yang Chang; Yu-Chuan Chuang; En-Jui Chang; An-Yeu Andy Wu (IEEE Trans. Computers, 2021)

T-EAP: Trainable Energy-Aware Pruning for NVM-based Computing-in-Memory Architecture. - Cheng-Yang Chang; Yu-Chuan Chuang; Kuang-Chao Chou; An-Yeu Wu (AICAS, 2022)

Automated Quantization Range Mapping for DAC/ADC Non-linearity in Computing-In-Memory. - Chi-Tse Huang; Yu-Chuan Chuang; Ming-Guang Lin; An-Yeu Andy Wu (ISCAS, 2022)

C3-SL: Circular Convolution-Based Batch-Wise Compression for Communication-Efficient Split Learning. - Cheng-Yen Hsieh; Yu-Chuan Chuang; An-Yeu Wu (MLSP, 2022)

D-NAT: Data-Driven Non-Ideality Aware Training Framework for Fabricated Computing-In-Memory Macros. - Ming-Guang Lin; Chi-Tse Huang; Yu-Chuan Chuang; Yi-Ta Chen; Ying-Tuan Hsu; Yu-Kai Chen; Jyun-Jhe Chou; Tsung-Te Liu; Chi-Sheng Shih 001; An-Yeu Wu (IEEE J. Emerg. Sel. Topics Circuits Syst., 2022)

BWA-NIMC: Budget-based Workload Allocation for Hybrid Near/In-Memory-Computing. - Chi-Tse Huang; Cheng-Yang Chang; Yu-Chuan Chuang; An-Yeu Andy Wu (DAC, 2023)

S-QRD-ELM: Scalable QR-Decomposition-Based Extreme Learning Machine Engine Supporting Online Class-Incremental Learning for ECG-Based User Identification. - Yi-Ta Chen; Yu-Chuan Chuang; Li-Sheng Chang; An-Yeu Wu (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

E-UPQ: Energy-Aware Unified Pruning-Quantization Framework for CIM Architecture. - Cheng-Yang Chang; Kuang-Chao Chou; Yu-Chuan Chuang; An-Yeu Wu (IEEE J. Emerg. Sel. Topics Circuits Syst., 2023)

Recent Progress and Development of Hyperdimensional Computing (HDC) for Edge Intelligence. - Cheng-Yang Chang; Yu-Chuan Chuang; Chi-Tse Huang; An-Yeu Wu (IEEE J. Emerg. Sel. Topics Circuits Syst., 2023)

Dynamic-HDC: A Two-Stage Dynamic Inference Framework for Brain-Inspired Hyperdimensional Computing. - Yu-Chuan Chuang; Cheng-Yang Chang; An-Yeu Wu (IEEE J. Emerg. Sel. Topics Circuits Syst., 2023)

BFP-CIM: Data-Free Quantization with Dynamic Block-Floating-Point Arithmetic for Energy-Efficient Computing-In-Memory-based Accelerator. - Cheng-Yang Chang; Chi-Tse Huang; Yu-Chuan Chuang; Kuang-Chao Chou; An-Yeu Andy Wu (ASPDAC, 2024)

A 40nm 24.6TOPS/W Scalable EfficientDet Processor for Object Detection. - Yu-Chuan Chuang; Ming-Guang Lin; Chi-Tse Huang; Chieh-Fang Teng; Cheng-Yang Chang; Yi-Ta Chen; An-Yeu Andy Wu (ISCAS, 2024)

BFP-CIM: Runtime Energy-Accuracy Scalable Computing-in-Memory-Based DNN Accelerator Using Dynamic Block-Floating-Point Arithmetic. - Cheng-Yang Chang; Chi-Tse Huang; Yu-Chuan Chuang; Kuang-Chao Chou; An-Yeu Wu (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

AIRCHITECT v2: Learning the Hardware Accelerator Design Space Through Unified Representations. - Jamin Seo; Akshat Ramachandran; Yu-Chuan Chuang; Anirudh Itagi; Tushar Krishna (DATE, 2025)