The Design and Performance Analysis of Embedded Parallel Multiprocessing System. - Guanghui Liu; Fei Xia; Xuejun Yang; Haifang Zhou; Heng Zhao; Yu Deng 001 (ICESS, 2004)

Matrix-Based Programming Optimization for Improving Memory Hierarchy Performance on Imagine. - Xuejun Yang; Jing Du 002; Xiaobo Yan; Yu Deng 001 (ISPA, 2006)

Implementation and Evaluation of Specific Data-Intensive Scientific Applications on the FT64 Stream Processor. - Yu Deng 001; Xuejun Yang; Xiaobo Yan; Ying Zhang 032; Jing Du 002 (CIT, 2007)

Laplace Transformation on the FT64 Stream Processor. - Yu Deng 001; Xuejun Yang; Xiaobo Yan; Kun Zeng (Asia-Pacific Computer Systems Architecture Conference, 2007)

Efficient generation of stream programs from loops. - Xuejun Yang; Yu Deng 001; Xiaobo Yan; Li Wang 027; Jing Du 002; Ying Zhang 032 (ICPADS, 2007)

Evaluation of Transcendental Functions on Imagine Architecture. - Xiaobo Yan; Tao Tang 001; Yu Deng 001; Jing Du 002; Xuejun Yang (ICPP, 2007)

A 64-bit stream processor architecture for scientific applications. - Xuejun Yang; Xiaobo Yan; Zuocheng Xing; Yu Deng 001; Jiang Jiang; Ying Zhang 032 (ISCA, 2007)

Implementation and Optimization of Sparse Matrix-Vector Multiplication on Imagine Stream Processor. - Li Wang 027; Xuejun Yang; Guibin Wang; Xiaobo Yan; Yu Deng 001; Jing Du 002; Ying Zhang 032; Tao Tang 001; Kun Zeng (ISPA, 2007)

A Double-Buffering Strategy for the SRF management in the Imagine Stream Processor. - Yu Deng 001; Li Wang 027; Xiaobo Yan; Xuejun Yang (ICYCS, 2008)

Scientific Computing Applications on a Stream Processor. - Ying Zhang 032; Xuejun Yang; Guibin Wang; Ian Rogers; Gen Li 002; Yu Deng 001; Xiaobo Yan (ISPASS, 2008)

Optimizing scientific application loops on stream processors. - Li Wang 027; Xuejun Yang; Jingling Xue; Yu Deng 001; Xiaobo Yan; Tao Tang 001; Quan Hoang Nguyen 001 (LCTES, 2008)

Comparability graph coloring for optimizing utilization of stream register files in stream processors. - Xuejun Yang; Li Wang 027; Jingling Xue; Yu Deng 001; Ying Zhang 032 (PPoPP, 2009)

SRF Coloring: Stream Register File Allocation via Graph Coloring. - Xuejun Yang; Yu Deng 001; Li Wang 027; Xiaobo Yan; Jing Du 002; Ying Zhang 032; Guibin Wang; Tao Tang 001 (J. Comput. Sci. Technol., 2009)

Matrix-based streamization approach for improving locality and parallelism on FT64 stream processor. - Xuejun Yang; Jing Du 002; Xiaobo Yan; Yu Deng 001 (J. Supercomput., 2009)

Fei Teng 64 Stream Processing System: Architecture, Compiler, and Programming. - Xuejun Yang; Xiaobo Yan; Zuocheng Xing; Yu Deng 001; Jiang Jiang; Jing Du 002; Ying Zhang 032 (IEEE Trans. Parallel Distributed Syst., 2009)

A Scalable and Fast Microprocessor Design Space Exploration Methodology. - Lei Wang 011; Yuxing Tang; Yu Deng 001; Fangyan Qin; Qiang Dou; Guangda Zhang; Feipeng Zhang (MCSoC, 2015)

The Macro-DSE for HPC Processing Unit: The Physical Constraints Perspective. - Yuxing Tang; Lei Wang 011; Yu Deng 001; Xiaoqiang Ni; Qiang Dou (GPC, 2016)

Laius: An 8-Bit Fixed-Point CNN Hardware Inference Engine. - Zhisheng Li; Lei Wang 011; Shasha Guo 001; Yu Deng 001; Qiang Dou; Haifang Zhou; Wenyuan Lu (ISPA/IUCC, 2017)

A Power Efficient Hardware Implementation of the IF Neuron Model. - Shuquan Wang; Shasha Guo 001; Lei Wang 001; Nan Li; Zikai Nie; Yu Deng 001; Qiang Dou; Weixia Xu (ACA, 2018)

A Parallel Algorithm for Instruction Dependence Graph Analysis Based on Multithreading. - Lei Wang 011; Yu Deng 001; Rui Gong; Wei Shi; Zhenyu Zhao; Qiang Dou (ISPA/IUCC/BDCloud/SocialCom/SustainCom, 2018)

Systolic Array Based Accelerator and Algorithm Mapping for Deep Learning Algorithms. - Zhijie Yang; Lei Wang 011; Dong Ding; Xiangyu Zhang; Yu Deng 001; Shiming Li; Qiang Dou (NPC, 2018)

ASIE: An Asynchronous SNN Inference Engine for AER Events Processing. - Ziyang Kang; Lei Wang 011; Shasha Guo 001; Rui Gong; Yu Deng 001; Qiang Dou (ASYNC, 2019)

A Systolic SNN Inference Accelerator and its Co-optimized Software Framework. - Shasha Guo 001; Lei Wang 011; Shuquan Wang; Yu Deng 001; Zhijie Yang; Shiming Li; Zhige Xie; Qiang Dou (ACM Great Lakes Symposium on VLSI, 2019)

Laius: an energy-efficient FPGA CNN accelerator with the support of a fixed-point training framework. - Zikai Nie; Zhisheng Li; Lei Wang 011; Shasha Guo 001; Yu Deng 001; Rangyu Deng; Qiang Dou (Int. J. Comput. Sci. Eng., 2020)

SIES: A Novel Implementation of Spiking Convolutional Neural Network Inference Engine on Field-Programmable Gate Array. - Shuquan Wang; Lei Wang 011; Yu Deng 001; Zhi-Jie Yang; Sha-Sha Guo 001; Ziyang Kang; Yu-Feng Guo; Weixia Xu (J. Comput. Sci. Technol., 2020)

ASIE: An Asynchronous SNN Inference Engine for AER Events Processing. - Ziyang Kang; Lei Wang 011; Shasha Guo 001; Rui Gong; Shiming Li; Yu Deng 001; Weixia Xu (ACM J. Emerg. Technol. Comput. Syst., 2020)

CSMO-DSE: Fast and Precise Application-driven DSE Guided by Criticality and Sensitivity Analysis. - Lei Wang 011; Yu Deng 001; Rui Gong; Wei Shi; Li Luo; Yongwen Wang (ACM J. Emerg. Technol. Comput. Syst., 2020)