An offset-tolerant current-sampling-based sense amplifier for Sub-100nA-cell-current nonvolatile memory. - Meng-Fan Chang; Shin-Jang Shen; Chia-Chi Liu; Che-Wei Wu; Yu-Fan Lin; Shang-Chi Wu; Chia-En Huang; Han-Chao Lai; Ya-Chin King; Chorng-Jung Lin; Hung-Jen Liao; Yu-Der Chih; et al. (ISSCC, 2011)

A 0.5V 4Mb logic-process compatible embedded resistive RAM (ReRAM) in 65nm CMOS using low-voltage current-mode sensing scheme with 45ns random read time. - Meng-Fan Chang; Che-Wei Wu; Chia-Chen Kuo; Shin-Jang Shen; Ku-Feng Lin; Shu-Meng Yang; Ya-Chin King; Chorng-Jung Lin; Yu-Der Chih (ISSCC, 2012)

Cycling endurance optimization scheme for 1Mb STT-MRAM in 40nm technology. - Hung-Chang Yu; Kai-Chun Lin; Ku-Feng Lin; Chin-Yi Huang; Yu-Der Chih; Tong-Chern Ong; Tsung-Yung Jonathan Chang; Sreedhar Natarajan; Luan C. Tran (ISSCC, 2013)

A 55-nm, 0.86-Volt operation, 75MHz high speed, 96uA/MHz low power, wide voltage supply range 2M-bit split-gate embedded Flash. - Caleb Y.-S. Cho; J. C. Wang; Lion Huang; Milo Weng; Yu-Fan Lin; Chia-Fu Lee; C. W. Lien; H. C. Feng; Tassa Yang; S. P. Liao; J. J. Wu; Yu-Der Chih; et al. (VLSI-DAT, 2013)

A 180 MHz direct access read 4.6Mb embedded flash in 90nm technology operating under wide range power supply from 2.1V to 3.6V. - Hung-Chang Yu; Ku-Feng Lin; Kai-Chun Lin; Yu-Der Chih; Sreedhar Natarajan (VLSI-DAT, 2013)

An Offset-Tolerant Fast-Random-Read Current-Sampling-Based Sense Amplifier for Small-Cell-Current Nonvolatile Memory. - Meng-Fan Chang; Shin-Jang Shen; Chia-Chi Liu; Che-Wei Wu; Yu-Fan Lin; Ya-Chin King; Chorng-Jung Lin; Hung-Jen Liao; Yu-Der Chih; Hiroyuki Yamauchi (IEEE J. Solid State Circuits, 2013)

A Low-Voltage Bulk-Drain-Driven Read Scheme for Sub-0.5 V 4 Mb 65 nm Logic-Process Compatible Embedded Resistive RAM (ReRAM) Macro. - Meng-Fan Chang; Che-Wei Wu; Chia-Chen Kuo; Shin-Jang Shen; Sue-Meng Yang; Ku-Feng Lin; Wen-Chao Shen; Ya-Chin King; Chorng-Jung Lin; Yu-Der Chih (IEEE J. Solid State Circuits, 2013)

19.4 embedded 1Mb ReRAM in 28nm CMOS with 0.27-to-1V read using swing-sample-and-couple sense amplifier and self-boost-write-termination scheme. - Meng-Fan Chang; Jui-Jen Wu; Tun-Fei Chien; Yen-Chen Liu; Ting-Chin Yang; Wen-Chao Shen; Ya-Chin King; Chorng-Jung Lin; Ku-Feng Lin; Yu-Der Chih; Sreedhar Natarajan; Tsung-Yung Jonathan Chang (ISSCC, 2014)

Area-Efficient Embedded Resistive RAM (ReRAM) Macros Using Logic-Process Vertical-Parasitic-BJT (VPBJT) Switches and Read-Disturb-Free Temperature-Aware Current-Mode Read Scheme. - Meng-Fan Chang; Chia-Chen Kuo; Shyh-Shyuan Sheu; Chorng-Jung Lin; Ya-Chin King; Frederick T. Chen; Tzu-Kun Ku; Ming-Jinn Tsai; Jui-Jen Wu; Yu-Der Chih (IEEE J. Solid State Circuits, 2014)

An Asymmetric-Voltage-Biased Current-Mode Sensing Scheme for Fast-Read Embedded Flash Macros. - Meng-Fan Chang; Yu-Fan Lin; Yen-Chen Liu; Jui-Jen Wu; Shin-Jang Shen; Wu-Chin Tsai; Yu-Der Chih (IEEE J. Solid State Circuits, 2015)

Low VDDmin Swing-Sample-and-Couple Sense Amplifier and Energy-Efficient Self-Boost-Write-Termination Scheme for Embedded ReRAM Macros Against Resistance and Switch-Time Variations. - Meng-Fan Chang; Jui-Jen Wu; Tun-Fei Chien; Yen-Chen Liu; Ting-Chin Yang; Wen-Chao Shen; Ya-Chin King; Chrong Jung Lin; Ku-Feng Lin; Yu-Der Chih; Tsung-Yung Jonathan Chang (IEEE J. Solid State Circuits, 2015)

A 1.4Mb 40-nm embedded ReRAM macro with 0.07um2 bit cell, 2.7mA/100MHz low-power read and hybrid write verify for high endurance application. - Chia-Fu Lee; Hon-Jarn Lin; Chiu-Wang Lien; Yu-Der Chih; Tsung-Yung Jonathan Chang (A-SSCC, 2017)

11.3 A 10nm 32Kb low-voltage logic-compatible anti-fuse one-time-programmable memory with anti-tampering sensing scheme. - Shau-Yu Chou; Yu-Shiang Chen; Jun-Hao Chang; Yu-Der Chih; Tsung-Yung Jonathan Chang (ISSCC, 2017)

11.2 A 1Mb embedded NOR flash memory with 39µW program power for mm-scale high-temperature sensor nodes. - Qing Dong 001; Yejoong Kim; Inhee Lee 001; Myungjoon Choi; Ziyun Li; Jingcheng Wang; Kaiyuan Yang 001; Yen-Po Chen; Junjie Dong; Minchang Cho; Gyouho Kim; Wei-Keng Chang; et al. (ISSCC, 2017)

Logic Process Compatible 40nm 256K×144 Embedded RRAM with Low Voltage Current Limiter and Ambient Compensation Scheme to Improve the Read Window. - Chien-An Lai; Chung-Cheng Chou; Chi-Hsiang Weng; Zheng-Jun Lin; Pei-Ling Tseng; Chien-Fan Wang; Chih-Chen Wang; Chin-I Su; Wei-Chi Chen; Yu-Cheng Lin; Tong-Chern Ong; Chi Chang; et al. (A-SSCC, 2018)

An N40 256K×44 embedded RRAM macro with SL-precharge SA and low-voltage current limiter to improve read and write performance. - Chung-Cheng Chou; Zheng-Jun Lin; Pei-Ling Tseng; Chih-Feng Li; Chih-Yang Chang; Wei-Chi Chen; Yu-Der Chih; Tsung-Yung Jonathan Chang (ISSCC, 2018)

A 1Mb 28nm STT-MRAM with 2.8ns read access time at 1.2V VDD using single-cap offset-cancelled sense amplifier and in-situ self-write-termination. - Qing Dong 001; Zhehong Wang; Jongyup Lim; Yiqun Zhang 002; Yi-Chun Shih; Yu-Der Chih; Tsung-Yung Jonathan Chang; David T. Blaauw; Dennis Sylvester (ISSCC, 2018)

Logic Process Compatible 40NM 16MB, Embedded Perpendicular-MRAM with Hybrid-Resistance Reference, Sub-μA Sensing Resolution, and 17.5NS Read Access Time. - Yi-Chun Shih; Chia-Fu Lee; Yen-An Chang; Po-Hao Lee; Hon-Jarn Lin; Yu-Lin Chen; Ku-Feng Lin; Ta-Ching Yeh; Hung-Chang Yu; Harry Chuang; Yu-Der Chih; Tsung-Yung Jonathan Chang (VLSI Circuits, 2018)

A 28NM Integrated True Random Number Generator Harvesting Entropy from MRAM. - Kaiyuan Yang 001; Qing Dong 001; Zhehong Wang; Yi-Chun Shih; Yu-Der Chih; Tsung-Yung Jonathan Chang; David T. Blaauw; Dennis Sylvester (VLSI Circuits, 2018)

A 1-Mb 28-nm 1T1MTJ STT-MRAM With Single-Cap Offset-Cancelled Sense Amplifier and In Situ Self-Write-Termination. - Qing Dong 001; Zhehong Wang; Jongyup Lim; Yiqun Zhang 002; Mahmut E. Sinangil; Yi-Chun Shih; Yu-Der Chih; Tsung-Yung Jonathan Chang; David T. Blaauw; Dennis Sylvester (IEEE J. Solid State Circuits, 2019)

A ReRAM Macro Using Dynamic Trip-Point-Mismatch Sampling Current-Mode Sense Amplifier and Low-DC Voltage-Mode Write-Termination Scheme Against Resistance and Write-Delay Variation. - Chieh-Pu Lo; Wen-Zhang Lin; Wei-Yu Lin; Huan-Ting Lin; Tzu-Hsien Yang; Yen-Ning Chiang; Ya-Chin King; Chrong Jung Lin; Yu-Der Chih; Tsung-Yung Jonathon Chang; Meng-Fan Chang (IEEE J. Solid State Circuits, 2019)

Logic Process Compatible 40-nm 16-Mb, Embedded Perpendicular-MRAM With Hybrid-Resistance Reference, Sub- $ mu$ A Sensing Resolution, and 17.5-nS Read Access Time. - Yi-Chun Shih; Chia-Fu Lee; Yen-An Chang; Po-Hao Lee; Hon-Jarn Lin; Yu-Lin Chen; Ku-Feng Lin; Ta-Ching Yeh; Hung-Chang Yu; Harry Chuang; Yu-Der Chih; Tsung-Yung Jonathan Chang (IEEE J. Solid State Circuits, 2019)

13.3 A 22nm 32Mb Embedded STT-MRAM with 10ns Read Speed, 1M Cycle Write Endurance, 10 Years Retention at 150°C and High Immunity to Magnetic Field Interference. - Yu-Der Chih; Yi-Chun Shih; Chia-Fu Lee; Yen-An Chang; Po-Hao Lee; Hon-Jarn Lin; Yu-Lin Chen; Chieh-Pu Lo; Meng-Chun Shih; Kuei-Hung Shen; Harry Chuang; Tsung-Yung Jonathan Chang (ISSCC, 2020)

A 22nm 96KX144 RRAM Macro with a Self-Tracking Reference and a Low Ripple Charge Pump to Achieve a Configurable Read Window and a Wide Operating Voltage Range. - Chung-Cheng Chou; Zheng-Jun Lin; Chien-An Lai; Chin-I Su; Pei-Ling Tseng; Wei-Chi Chen; Wu-Chin Tsai; Wen-Ting Chu; Tong-Chern Ong; Harry Chuang; Yu-Der Chih; Tsung-Yung Jonathan Chang (VLSI Circuits, 2020)

An All-Weights-on-Chip DNN Accelerator in 22nm ULL Featuring 24×1 Mb eRRAM. - Zhehong Wang; Ziyun Li; Li Xu 006; Qing Dong 001; Chin-I Su; Wen-Ting Chu; George Tsou; Yu-Der Chih; Tsung-Yung Jonathan Chang; Dennis Sylvester; Hun-Seok Kim; David T. Blaauw (VLSI Circuits, 2020)

A 40nm 100Kb 118.44TOPS/W Ternary-weight Computein-Memory RRAM Macro with Voltage-sensing Read and Write Verification for reliable multi-bit RRAM operation. - Jong-Hyeok Yoon; Muya Chang; Win-San Khwa; Yu-Der Chih; Meng-Fan Chang; Arijit Raychowdhury (CICC, 2021)

An 89TOPS/W and 16.3TOPS/mm2 All-Digital SRAM-Based Full-Precision Compute-In Memory Macro in 22nm for Machine-Learning Edge Applications. - Yu-Der Chih; Po-Hao Lee; Hidehiro Fujiwara; Yi-Chun Shih; Chia-Fu Lee; Rawan Naous; Yu-Lin Chen; Chieh-Pu Lo; Cheng-Han Lu; Haruki Mori; Wei-Cheng Zhao; Dar Sun; et al. (ISSCC, 2021)

A 22nm 4Mb 8b-Precision ReRAM Computing-in-Memory Macro with 11.91 to 195.7TOPS/W for Tiny AI Edge Devices. - Cheng-Xin Xue; Je-Min Hung; Hui-Yao Kao; Yen-Hsiang Huang; Sheng-Po Huang; Fu-Chun Chang; Peng Chen; Ta-Wei Liu; Chuan-Jia Jhang; Chin-I Su; Win-San Khwa; Chung-Chuan Lo; et al. (ISSCC, 2021)

29.1 A 40nm 64Kb 56.67TOPS/W Read-Disturb-Tolerant Compute-in-Memory/Digital RRAM Macro with Active-Feedback-Based Read and In-Situ Write Verification. - Jong-Hyeok Yoon; Muya Chang; Win-San Khwa; Yu-Der Chih; Meng-Fan Chang; Arijit Raychowdhury (ISSCC, 2021)

A 16Kb Antifuse One-Time-Programmable Memory in 5nm High-K Metal-Gate Fin-FET CMOS Featuring Bootstrap High Voltage Scheme, Read Endpoint Detection and Pseudo-Differential Sensing. - Shaun Chou; Gu-Huan Li; Shawn Chen; Jun-Hao Chang; Wan-Hsueh Cheng; Shao-Ding Wu; Philex Fan; Chia-En Huang; Yu-Der Chih; Yih Wang; Jonathan Chang (VLSI Circuits, 2021)

RRAM-DNN: An RRAM and Model-Compression Empowered All-Weights-On-Chip DNN Accelerator. - Ziyun Li; Zhehong Wang; Li Xu 006; Qing Dong 001; Bowen Liu 001; Chin-I Su; Wen-Ting Chu; George Tsou; Yu-Der Chih; Tsung-Yung Jonathan Chang; Dennis Sylvester; Hun-Seok Kim; et al. (IEEE J. Solid State Circuits, 2021)

A 40nm 60.64TOPS/W ECC-Capable Compute-in-Memory/Digital 2.25MB/768KB RRAM/SRAM System with Embedded Cortex M3 Microprocessor for Edge Recommendation Systems. - Muya Chang; Samuel D. Spetalnick; Brian Crafton; Win-San Khwa; Yu-Der Chih; Meng-Fan Chang; Arijit Raychowdhury (ISSCC, 2022)

A 22nm 4Mb STT-MRAM Data-Encrypted Near-Memory Computation Macro with a 192GB/s Read-and-Decryption Bandwidth and 25.1-55.1TOPS/W 8b MAC for AI Operations. - Yen-Cheng Chiu; Chia-Sheng Yang; Shih-Hsih Teng; Hsiao-Yu Huang; Fu-Chun Chang; Yuan Wu 009; Yu-An Chien; Fang-Ling Hsieh; Chung-Yuan Li; Guan-Yi Lin; Po-Jung Chen; Tsen-Hsiang Pan; et al. (ISSCC, 2022)

A 5-nm 254-TOPS/W 221-TOPS/mm2 Fully-Digital Computing-in-Memory Macro Supporting Wide-Range Dynamic-Voltage-Frequency Scaling and Simultaneous MAC and Write Operations. - Hidehiro Fujiwara; Haruki Mori; Wei-Chang Zhao; Mei-Chen Chuang; Rawan Naous; Chao-Kai Chuang; Takeshi Hashizume; Dar Sun; Chia-Fu Lee; Kerem Akarvardar; Saman Adham; Tan-Li Chou; et al. (ISSCC, 2022)

An 8-Mb DC-Current-Free Binary-to-8b Precision ReRAM Nonvolatile Computing-in-Memory Macro using Time-Space-Readout with 1286.4-21.6TOPS/W for Edge-AI Devices. - Je-Min Hung; Yen-Hsiang Huang; Sheng-Po Huang; Fu-Chun Chang; Tai-Hao Wen; Chin-I Su; Win-San Khwa; Chung-Chuan Lo; Ren-Shuo Liu; Chih-Cheng Hsieh; Kea-Tiong Tang; Yu-Der Chih; et al. (ISSCC, 2022)

A 40nm 64kb 26.56TOPS/W 2.37Mb/mm2RRAM Binary/Compute-in-Memory Macro with 4.23x Improvement in Density and >75% Use of Sensing Dynamic Range. - Samuel D. Spetalnick; Muya Chang; Brian Crafton; Win-San Khwa; Yu-Der Chih; Meng-Fan Chang; Arijit Raychowdhury (ISSCC, 2022)

A 12nm 121-TOPS/W 41.6-TOPS/mm2 All Digital Full Precision SRAM-based Compute-in-Memory with Configurable Bit-width For AI Edge Applications. - Chia-Fu Lee; Cheng-Han Lu; Cheng-En Lee; Haruki Mori; Hidehiro Fujiwara; Yi-Chun Shih; Tan-Li Chou; Yu-Der Chih; Tsung-Yung Jonathan Chang (VLSI Technology and Circuits, 2022)

A 22-nm 1-Mb 1024-b Read Data-Protected STT-MRAM Macro With Near-Memory Shift-and-Rotate Functionality and 42.6-GB/s Read Bandwidth for Security-Aware Mobile Device. - Yen-Cheng Chiu; Tung-Cheng Chang; Chun-Ying Lee; Je-Min Hung; Kuang-Tang Chang; Cheng-Xin Xue; Ssu-Yen Wu; Hui-Yao Kao; Peng Chen; Hsiao-Yu Huang; Shih-Hsih Teng; Chieh-Pu Lo; et al. (IEEE J. Solid State Circuits, 2022)

CHIMERA: A 0.92-TOPS, 2.2-TOPS/W Edge AI Accelerator With 2-MByte On-Chip Foundry Resistive RAM for Efficient Training and Inference. - Kartik Prabhu; Albert Gural; Zainab F. Khan; Robert M. Radway; Massimo Giordano; Kalhan Koul; Rohan Doshi; John W. Kustin; Timothy Liu; Gregorio B. Lopes; Victor Turbiner; Win-San Khwa; et al. (IEEE J. Solid State Circuits, 2022)

A 40-nm, 64-Kb, 56.67 TOPS/W Voltage-Sensing Computing-In-Memory/Digital RRAM Macro Supporting Iterative Write With Verification and Online Read-Disturb Detection. - Jong-Hyeok Yoon; Muya Chang; Win-San Khwa; Yu-Der Chih; Meng-Fan Chang; Arijit Raychowdhury (IEEE J. Solid State Circuits, 2022)

A 40-nm 118.44-TOPS/W Voltage-Sensing Compute-in-Memory RRAM Macro With Write Verification and Multi-Bit Encoding. - Jong-Hyeok Yoon; Muya Chang; Win-San Khwa; Yu-Der Chih; Meng-Fan Chang; Arijit Raychowdhury (IEEE J. Solid State Circuits, 2022)

EMBER: A 100 MHz, 0.86 mm2, Multiple-Bits-per-Cell RRAM Macro in 40 nm CMOS with Compact Peripherals and 1.0 pJ/bit Read Circuitry. - Luke R. Upton; Akash Levy; Michael D. Scott 002; Dennis Rich; Win-San Khwa; Yu-Der Chih; Meng-Fan Chang; Subhasish Mitra; Priyanka Raina; Boris Murmann (ESSCIRC, 2023)

A 73.53TOPS/W 14.74TOPS Heterogeneous RRAM In-Memory and SRAM Near-Memory SoC for Hybrid Frame and Event-Based Target Tracking. - Muya Chang; Ashwin Sanjay Lele; Samuel D. Spetalnick; Brian Crafton; Shota Konno; Zishen Wan; Ashwin Bhat; Win-San Khwa; Yu-Der Chih; Meng-Fan Chang; Arijit Raychowdhury (ISSCC, 2023)

A 22nm 8Mb STT-MRAM Near-Memory-Computing Macro with 8b-Precision and 46.4-160.1TOPS/W for Edge-AI Devices. - Yen-Cheng Chiu; Win-San Khwa; Chung-Yuan Li; Fang-Ling Hsieh; Yu-An Chien; Guan-Yi Lin; Po-Jung Chen; Tsen-Hsiang Pan; De-Qi You; Fang-Yi Chen; Andrew Lee; Chung-Chuan Lo; et al. (ISSCC, 2023)

A Nonvolatile Al-Edge Processor with 4MB SLC-MLC Hybrid-Mode ReRAM Compute-in-Memory Macro and 51.4-251TOPS/W. - Wei-Hsing Huang; Tai-Hao Wen; Je-Min Hung; Win-San Khwa; Yun-Chen Lo; Chuan-Jia Jhang; Hung-Hsi Hsu; Yu-Hsiang Chin; Yu-Chiao Chen; Chuna-Chuan Lo; Ren-Shuo Liu; Kea-Tiong Tang; et al. (ISSCC, 2023)

A 16nm 32Mb Embedded STT-MRAM with a 6ns Read-Access Time, a 1M-Cycle Write Endurance, 20-Year Retention at 150°C and MTJ-OTP Solutions for Magnetic Immunity. - Po-Hao Lee; Chia-Fu Lee; Yi-Chun Shih; Hon-Jarn Lin; Yen-An Chang; Cheng-Han Lu; Yu-Lin Chen; Chieh-Pu Lo; Chung-Chieh Chen; Cheng-Hsiung Kuo; Tan-Li Chou; Chia-Yu Wang; et al. (ISSCC, 2023)

A 4nm 6163-TOPS/W/b $ mathbf{4790-TOPS/mm^{2}/b}$ SRAM Based Digital-Computing-in-Memory Macro Supporting Bit-Width Flexibility and Simultaneous MAC and Weight Update. - Haruki Mori; Wei-Chang Zhao; Cheng-En Lee; Chia-Fu Lee; Yu-Hao Hsu; Chao-Kai Chuang; Takeshi Hashizume; Hao-Chun Tung; Yao-Yi Liu; Shin-Rung Wu; Kerem Akarvardar; Tan-Li Chou; et al. (ISSCC, 2023)

A 2.38 MCells/mm2 9.81 -350 TOPS/W RRAM Compute-in-Memory Macro in 40nm CMOS with Hybrid Offset/IOFF Cancellation and ICELL RBLSL Drop Mitigation. - Samuel D. Spetalnick; Muya Chang; Shota Konno; Brian Crafton; Ashwin Sanjay Lele; Win-San Khwa; Yu-Der Chih; Meng-Fan Chang; Arijit Raychowdhury (VLSI Technology and Circuits, 2023)

A 28nm Nonvolatile AI Edge Processor using 4Mb Analog-Based Near-Memory-Compute ReRAM with 27.2 TOPS/W for Tiny AI Edge Devices. - Tai-Hao Wen; Je-Min Hung; Hung-Hsi Hsu; Yuan Wu 009; Fu-Chun Chang; Chung-Yuan Li; Chih-Han Chien; Chin-I Su; Win-San Khwa; Jui-Jen Wu; Chung-Chuan Lo; Ren-Shuo Liu; et al. (VLSI Technology and Circuits, 2023)

8-b Precision 8-Mb ReRAM Compute-in-Memory Macro Using Direct-Current-Free Time-Domain Readout Scheme for AI Edge Devices. - Je-Min Hung; Tai-Hao Wen; Yen-Hsiang Huang; Sheng-Po Huang; Fu-Chun Chang; Chin-I Su; Win-San Khwa; Chung-Chuan Lo; Ren-Shuo Liu; Chih-Cheng Hsieh; Kea-Tiong Tang; Yu-Der Chih; et al. (IEEE J. Solid State Circuits, 2023)

34.4 A 3nm, 32.5TOPS/W, 55.0TOPS/mm2 and 3.78Mb/mm2 Fully-Digital Compute-in-Memory Macro Supporting INT12 × INT12 with a Parallel-MAC Architecture and Foundry 6T-SRAM Bit Cell. - Hidehiro Fujiwara; Haruki Mori; Wei-Chang Zhao; Kinshuk Khare; Cheng-En Lee; Xiaochen Peng; Vineet Joshi; Chao-Kai Chuang; Shu-Huan Hsu; Takeshi Hashizume; Toshiaki Naganuma; Chen-Hung Tien; et al. (ISSCC, 2024)

15.7 A 32Mb RRAM in a 12nm FinFet Technology with a 0.0249μm2 Bit-Cell, a 3.2GB/S Read Throughput, a 10KCycle Write Endurance and a 10-Year Retention at 105°C. - Yi-Cheng Huang; Shang-Hsuan Liu; Hsu-Shun Chen; Hsin-Chang Feng; Chih-Feng Li; Chou-Ying Yang; Wei-Keng Chang; Chang-Feng Yang; Chun-Yu Wu; Yen-Cheng Lin; Tsung-Tse Yang; Chih-Yang Chang; et al. (ISSCC, 2024)

15.9 A 16nm 16Mb Embedded STT-MRAM with a 20ns Write Time, a 1012 Write Endurance and Integrated Margin-Expansion Schemes. - Ku-Feng Lin; Hiroki Noguchi; Yi-Chun Shih; Perng-Fei Yuh; Yuan-Jen Lee; Tung-Cheng Chang; Sheng-Po Huang; Yu-Fan Lin; Chun-Ying Lee; Yen-Hsiang Huang; Jui-Che Tsai; Saman Adham; et al. (ISSCC, 2024)

30.1 A 40nm VLIW Edge Accelerator with 5MB of 0.256pJ/b RRAM and a Localization Solver for Bristle Robot Surveillance. - Samuel D. Spetalnick; Ashwin Sanjay Lele; Brian Crafton; Muya Chang; Sigang Ryu; Jong-Hyeok Yoon; Zhijian Hao; Azadeh Ansari; Win-San Khwa; Yu-Der Chih; Meng-Fan Chang; Arijit Raychowdhury (ISSCC, 2024)

34.8 A 22nm 16Mb Floating-Point ReRAM Compute-in-Memory Macro with 31.2TFLOPS/W for AI Edge Devices. - Tai-Hao Wen; Hung-Hsi Hsu; Win-San Khwa; Wei-Hsing Huang; Zhao-En Ke; Yu-Hsiang Chin; Hua-Jin Wen; Yu-Chen Chang; Wei-Ting Hsu; Chung-Chuan Lo; Ren-Shuo Liu; Chih-Cheng Hsieh; et al. (ISSCC, 2024)

MINOTAUR: An Edge Transformer Inference and Training Accelerator with 12 MBytes On-Chip Resistive RAM and Fine-Grained Spatiotemporal Power Gating. - Kartik Prabhu; Robert M. Radway; Y. Jeffrey; Kai Bartolone; Massimo Giordano; Fabian Peddinghaus; Yonatan Urman; Win-San Khwa; Yu-Der Chih; Meng-Fan Chang; Subhasish Mitra; Priyanka Raina (VLSI Technology and Circuits, 2024)

A 22nm Nonvolatile AI-Edge Processor with 21.4TFLOPS/W using 47.25Mb Lossless-Compressed-Computing STT-MRAM Near-Memory-Compute Macro. - De-Qi You; Win-San Khwa; Jui-Jen Wu; Chuan-Jia Jhang; Guan-Yi Lin; Po-Jung Chen; Ting-Chien Chiu; Fang-Yi Chen; Andrew Lee; Yu-Cheng Hung; Chung-Chuan Lo; Ren-Shuo Liu; et al. (VLSI Technology and Circuits, 2024)

A Nonvolatile AI-Edge Processor With SLC-MLC Hybrid ReRAM Compute-in-Memory Macro Using Current-Voltage-Hybrid Readout Scheme. - Hung-Hsi Hsu; Tai-Hao Wen; Wei-Hsing Huang; Win-San Khwa; Yun-Chen Lo; Chuan-Jia Jhang; Yu-Hsiang Chin; Yu-Chiao Chen; Chung-Chuan Lo; Ren-Shuo Liu; Kea-Tiong Tang; Chih-Cheng Hsieh; et al. (IEEE J. Solid State Circuits, 2024)

A Heterogeneous RRAM In-Memory and SRAM Near-Memory SoC for Fused Frame and Event-Based Target Identification and Tracking. - Ashwin Sanjay Lele; Muya Chang; Samuel D. Spetalnick; Brian Crafton; Shota Konno; Zishen Wan; Ashwin Bhat; Win-San Khwa; Yu-Der Chih; Meng-Fan Chang; Arijit Raychowdhury (IEEE J. Solid State Circuits, 2024)

An 8b-Precision 8-Mb STT-MRAM Near-Memory-Compute Macro Using Weight-Feature and Input-Sparsity Aware Schemes for Energy-Efficient Edge AI Devices. - De-Qi You; Yen-Cheng Chiu; Win-San Khwa; Chung-Yuan Li; Fang-Ling Hsieh; Yu-An Chien; Chung-Chuan Lo; Ren-Shuo Liu; Chih-Cheng Hsieh; Kea-Tiong Tang; Yu-Der Chih; Tsung-Yung Jonathan Chang; et al. (IEEE J. Solid State Circuits, 2024)

Efficient Processing of MLPerf Mobile Workloads Using Digital Compute-In-Memory Macros. - Xiaoyu Sun 001; Weidong Cao 001; Brian Crafton; Kerem Akarvardar; Haruki Mori; Hidehiro Fujiwara; Hiroki Noguchi; Yu-Der Chih; Meng-Fan Chang; Yih Wang; Tsung-Yung Jonathan Chang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

EMBER: Efficient Multiple-Bits-Per-Cell Embedded RRAM Macro for High-Density Digital Storage. - Akash Levy; Luke R. Upton; Michael D. Scott 002; Dennis Rich; Win-San Khwa; Yu-Der Chih; Meng-Fan Chang; Subhasish Mitra; Boris Murmann; Priyanka Raina (IEEE J. Solid State Circuits, 2024)

14.1 A 22nm 104.5TOPS/W µ-NMC-Δ-IMC Heterogeneous STT-MRAM CIM Macro for Noise-Tolerant Bayesian Neural Networks. - De-Qi You; Win-San Khwa; Bo Zhang; Fang-Yi Chen; Andrew Lee; Yu-Cheng Hung; Yi-Ming Li; Yu-Hui Wang; Chung-Chuan Lo; Ren-Shuo Liu; Kea-Tiong Tang; Chih-Cheng Hsieh; et al. (ISSCC, 2025)

A 22 nm Floating-Point ReRAM Compute-in-Memory Macro Using Residue-Shared ADC for AI Edge Device. - Hung-Hsi Hsu; Tai-Hao Wen; Win-San Khwa; Wei-Hsing Huang; Zhao-En Ke; Yu-Hsiang Chin; Hua-Jin Wen; Yu-Chen Chang; Wei-Ting Hsu; Ashwin Sanjay Lele; Bo Zhang; Ping-Sheng Wu; et al. (IEEE J. Solid State Circuits, 2025)

An Edge Accelerator With 5 MB of 0.256-pJ/bit Embedded RRAM and a Localization Solver for Bristle Robot Surveillance. - Samuel D. Spetalnick; Ashwin Sanjay Lele; Brian Crafton; Muya Chang; Sigang Ryu; Jong-Hyeok Yoon; Zhijian Hao; Azadeh Ansari; Win-San Khwa; Yu-Der Chih; Meng-Fan Chang; Arijit Raychowdhury (IEEE J. Solid State Circuits, 2025)

MINOTAUR: A Posit-Based 0.42-0.50-TOPS/W Edge Transformer Inference and Training Accelerator. - Kartik Prabhu; Robert M. Radway; Jeffrey Yu; Kai Bartolone; Massimo Giordano; Fabian Peddinghaus; Yonatan Urman; Win-San Khwa; Yu-Der Chih; Meng-Fan Chang; Subhasish Mitra; Priyanka Raina (IEEE J. Solid State Circuits, 2025)