Tracers placement for IP traceback against DDoS attacks. - Chun-Hsin Wang; Chang-Wu Yu 001; Chiu-Kuo Liang; Kun-Ming Yu; Wen Ouyang; Ching-Hsien Hsu; Yu-Guang Chen (IWCMC, 2006)

A novel fuzzy direct torque control system for three-level inverter-fed induction machine. - Shuxi Liu; Mingyu Wang; Yu-Guang Chen; Shan Li (Int. J. Autom. Comput., 2010)

NBTI-aware power gating design. - Ming-Chao Lee; Yu-Guang Chen; Ding-Kei Huang; Shih-Chieh Chang (ASP-DAC, 2011)

Efficient multiple-bit retention register assignment for power gated design: Concept and algorithms. - Yu-Guang Chen; Yiyu Shi 001; Kuan-Yu Lai; Hui Geng; Shih-Chieh Chang (ICCAD, 2012)

Efficient on-line module-level wake-up scheduling for high performance multi-module designs. - Ming-Chao Lee; Yiyu Shi 001; Yu-Guang Chen; Diana Marculescu; Shih-Chieh Chang (ISPD, 2012)

Critical Path Monitor Enabled Dynamic Voltage Scaling for Graceful Degradation in Sub-Threshold Designs. - Yu-Guang Chen; Tao Wang; Kuan-Yu Lai; Wan-Yu Wen; Yiyu Shi 001; Shih-Chieh Chang (DAC, 2014)

Yield and timing constrained spare TSV assignment for three-dimensional integrated circuits. - Yu-Guang Chen; Kuan-Yu Lai; Ming-Chao Lee; Yiyu Shi 001; Wing-Kai Hon; Shih-Chieh Chang (DATE, 2014)

Multibit Retention Registers for Power Gated Designs: Concept, Design, and Deployment. - Yu-Guang Chen; Hui Geng; Kuan-Yu Lai; Yiyu Shi 001; Shih-Chieh Chang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014)

Q-Learning Based Dynamic Voltage Scaling for Designs with Graceful Degradation. - Yu-Guang Chen; Wan-Yu Wen; Tao Wang; Yiyu Shi 001; Shih-Chieh Chang (ISPD, 2015)

Novel Spare TSV Deployment for 3-D ICs Considering Yield and Timing Constraints. - Yu-Guang Chen; Wan-Yu Wen; Yiyu Shi 001; Wing-Kai Hon; Shih-Chieh Chang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015)

A novel low-cost dynamic logic reconfigurable structure strategy for low power optimization. - Yu-Guang Chen; Wan-Yu Wen; Yun-Ting Wang; You-Luen Lee; Shih-Chieh Chang (ASP-DAC, 2016)

Pattern based runtime voltage emergency prediction: An instruction-aware block sparse compressed sensing approach. - Yu-Guang Chen; Michihiro Shintani; Takashi Sato 001; Yiyu Shi 001; Shih-Chieh Chang (ASP-DAC, 2017)

An efficient NBTI-aware wake-up strategy for power-gated designs. - Kun-Wei Chiu; Yu-Guang Chen; Ing-Chao Lin (DATE, 2018)

ROAD: Improving Reliability of Multi-core System via Asymmetric Aging. - Yu-Guang Chen; Ing-Chao Lin; Jian-Ting Ke (ICCAD, 2019)

Exploration and Exploitation of Dual Timing Margins for Improving Power Efficiency of Variable-Latency Designs. - Ning-Chi Huang; Yu-Guang Chen; Kai-Chiang Wu (ISVLSI, 2019)

Power Distribution Network Generation for Optimizing IR-Drop Aware Timing. - Wen-Hsiang Chang; Li-Yi Lin; Yu-Guang Chen; Mango C.-T. Chao (ICCAD, 2020)

An Artificial Neuron Network Based Chip Health Assessment Framework for IC Recycling. - Yu-Guang Chen (ICCE-TW, 2020)

Selective Sensor Placement for Cost-Effective Online Aging Monitoring and Resilience. - Hao-Chun Chang; Li-An Huang; Kai-Chiang Wu; Yu-Guang Chen (ISPD, 2020)

An NBTI-aware Task Parallelism Scheme for Improving Lifespan of Multi-core Systems. - Yu-Guang Chen; Yu-Yi Lin; Ing-Chao Lin (ISQED, 2020)

An Aging-Aware CMOS SRAM Structure Design for Boolean Logic In-Memory Computing. - Wei Chang; Yu-Guang Chen; Po-Yeh Huang; Jin-Fu Li 001 (DFT, 2021)

Overview of 2021 CAD Contest at ICCAD. - Tsung-Wei Huang; Yu-Guang Chen; Chun-Yao Wang; Takashi Sato 001 (ICCAD, 2021)

A Reconfigurable Accelerator Design for Quantized Depthwise Separable Convolutions. - Yu-Guang Chen; Hung-Yi Chiang; Chi-Wei Hsu; Tsung-Han Hsieh; Jing-Yang Jou (ISOCC, 2021)

A Novel NBTI-Aware Chip Remaining Lifetime Prediction Framework Using Machine Learning. - Yu-Guang Chen; Ing-Chao Lin; Yong-Che Wei (ISQED, 2021)

A Hierarchical and Reconfigurable Process Element Design for Quantized Neural Networks. - Yu-Guang Chen; Chi-Wei Hsu; Hung-Yi Chiang; Tsung-Han Hsieh; Jing-Yang Jou (SoCC, 2021)

An efficient NBTI-aware wake-up strategy: Concept, design, and manipulation. - Yu-Guang Chen; Ing-Chao Lin; Kun-Wei Chiu; Cheng-Hsuan Liu (Integr., 2021)

A Novel DNN Accelerator for Light-weight Neural Networks: Concept and Design. - Yu-Guang Chen; Tsung-Han Hsieh; Yi-Chen Ho; Jing-Yang Jou (AICAS, 2022)

Overview of 2022 CAD Contest at ICCAD. - Yu-Guang Chen; Chun-Yao Wang; Tsung-Wei Huang; Takashi Sato 001 (ICCAD, 2022)

An Aging Detection and Tolerance Framework for 8T SRAM Dot Product CIM Engine. - Yu-Guang Chen; Chi-Hsu Wang; Ing-Chao Lin (ISOCC, 2022)

DOC: A Novel DOuble-Contour-Based Macro Placement Framework for Mixed-Size Designs. - Yin-Rong Zhuo; Hui-Lin Chen; Yu-Guang Chen (APSIPA ASC, 2023)

An On-Line Aging Detection and Tolerance Framework for Improving Reliability of STT-MRAMs. - Yu-Guang Chen; Po-Yeh Huang; Jin-Fu Li 001 (ASP-DAC, 2023)

Reliability of Computing-In-Memories: Threats, Detection Methods, and Mitigation Approaches. - Yu-Guang Chen; Ying-Jing Tsai (DFT, 2023)

DRC Violation Prediction with Pre-global-routing Features Through Convolutional Neural Network. - Jhen-Gang Lin; Yu-Guang Chen; Yun-Wei Yang; Wei-Tse Hung; Cheng-Hong Tsai; De-Shiun Fu; Mango Chia-Tso Chao (ACM Great Lakes Symposium on VLSI, 2023)

Invited Paper: Overview of 2023 CAD Contest at ICCAD. - Takashi Sato 001; Chun-Yao Wang; Yu-Guang Chen; Tsung-Wei Huang (ICCAD, 2023)

DRC Violation Prediction After Global Route Through Convolutional Neural Network. - Wei-Tse Hung; Yu-Guang Chen; Jhen-Gang Lin; Yun-Wei Yang; Cheng-Hong Tsai; Mango Chia-Tso Chao (IEEE Trans. Very Large Scale Integr. Syst., 2023)

TNSS: Two-Nibble Sparsity-Aware Stride-Decomposing Acceleration for Convolutional Neural Networks. - Yun-Yin Huang; Yu-Guang Chen; Jing-Yang Jou (APCCAS, 2024)

Special Session: Overcoming Transient Faults and Aging Effects in Digital Computing-in-Memory Architectures: Detection, Tolerance, and Mitigation Strategies. - Yu-Guang Chen; Ting-Yi Wu (DFT, 2024)

GNN-Based INC and IVC Co-Optimization for Aging Mitigation. - Yu-Guang Chen; Hsiu-Yi Yang; Ing-Chao Lin (ETS, 2024)

Using Deep Neural Networks Analyzing Wound Images for Forensic Tool Mark Identification. - Chun-Ta Wei; Jeff Cheng-Lung Lee; Yu-Guang Chen; Wei-Hung Lin; Hui-Tzu Ting; Chi-Tse Pai (ICCE-Taiwan, 2024)

Enhancing Stability in CRPs: A Novel Parallel Scan-Chain PUF Design Considering Aging Effects. - Yu-Guang Chen; Tzong-Ying Lee; Yi-Ting Lin (ISCAS, 2024)

IR-drop and Routing Congestion Aware PDN Refinement Framework for Timing Optimization. - Yu-Guang Chen; Hung-Han Chang; Yu-Chuan Liang; Wen-Hsiang Chang; I-Ching Tsai; Chih-Wei Lin; Yun-Chih Chang; Mango Chia-Tso Chao (ISOCC, 2024)

CARDS: A Novel Detailed Macro Placement Framework for Minimizing Wirelength. - Yen-Lin Chua; Meng-Shan Wu; Yu-Guang Chen (ISOCC, 2024)

Exploring a Hybrid SRAM-RRAM Computing-In-Memory Architecture for DNNs Model Inference. - Yu-Guang Chen; Zhi-Wei Liu; Ying-Jing Tsai (ISVLSI, 2024)

Aging Mitigation in Systolic Array Accelerators: Balancing PE Loads for Enhanced Reliability. - Yu-Guang Chen; Yi-Chen Ho; Jing-Yang Jou (SOCC, 2024)

Aging-Aware Energy-Efficient Task Deployment of Heterogeneous Multicore Systems. - Yu-Guang Chen; Chieh-Shih Wang; Ing-Chao Lin; Zheng-Wei Chen; Ulf Schlichtmann (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

FastGDBN: A GPU-Accelerated DNN for Identifying Good Dies in Bad Neighborhoods. - Yu-Heng Tsao; Yu-Guang Chen (ETS, 2025)

Overcoming Training Data Scarcity in Routing Demand Prediction via Ensemble Learning. - Yu-Guang Chen; Shih-Cheng Huang; Cheng-Hong Tsai; De-Shiun Fu; Mango Chia-Tso Chao (ACM Great Lakes Symposium on VLSI, 2025)

Optimizing Reliability and Energy Efficiency in Heterogeneous Multicore Systems: A Novel Task Deployment Strategy. - Yu-Guang Chen; Yin-Rong Zhuo; Zheng-Wei Chen; Ing-Chao Lin (ACM Great Lakes Symposium on VLSI, 2025)

Basis Sharing: Cross-Layer Parameter Sharing for Large Language Model Compression. - Jingcun Wang; Yu-Guang Chen; Ing-Chao Lin; Bing Li 005; Grace Li Zhang (ICLR, 2025)

CIM for Transformer Models: Enhancing Large Language Model Inference Efficiency. - Meng-Syuan Li; Jung-Fang Ke; En-Ming Huang; Zhi-Wei Liu; Yu-Guang Chen; Chun-Yi Lee (ISVLSI, 2025)