A 20 Gbps Scalable Load Balanced Birkhoff-von Neumann Symmetric TDM Switch IC with SERDES Interfaces. - Yu-Hao Hsu; Min-Sheng Kao; Hou-Cheng Tzeng; Ching-Te Chiu; Jen-Ming Wu; Shuo-Hung Hsu (ASP-DAC, 2007)

A Scalable Load Balanced Birkhoff-von Neumann Symmetric TDM Switch IC for High-Speed Networking Applications. - Ching-Te Chiu; Yu-Hao Hsu; Min-Sheng Kao; Hou-Cheng Tzeng; Ming-Chang Du; Ping-Ling Yang; Ming-Hao Lu; Fanta Chen; Hung-Yu Lin; Jen-Ming Wu; Shuo-Hung Hsu; Yarsun Hsu (ISCAS, 2007)

A 28Gbps 4×4 switch with low jitter SerDes using area-saving RF model in 0.13µm CMOS technology. - Yu-Hao Hsu; Ming-Hao Lu; Ping-Ling Yang; Fanta Chen; You-Hung Li; Min-Sheng Kao; Chih-Hsing Lin; Ching-Te Chiu; Jen-Ming Wu; Shuo-Hung Hsu; Yarsun Hsu (ISCAS, 2008)

A Dynamic Frame Sizing Algorithm for CICQ Switches with 100% Throughput. - Cheng-Shang Chang; Yu-Hao Hsu; Jay Cheng; Duan-Shin Lee (INFOCOM, 2009)

A 32Gbps low propagation delay 4×4 switch IC for feedback-based system in 0.13μm CMOS technology. - Yu-Hao Hsu; Yang-Syu Lin; Ching-Te Chiu; Jen-Ming Wu; Shuo-Hung Hsu; Fanta Chen; Min-Sheng Kao; Yarsun Hsu (ISCAS, 2010)

A 32Gbps low propagation delay 4×4 switch IC for feedback-based system in 0.13μm CMOS technology. - Yu-Hao Hsu; Yang-Syu Lin; Ching-Te Chiu; Jen-Ming Wu; Shuo-Hung Hsu; Fanta Chen; Min-Sheng Kao; Wei-Chih Lai; Yarsun Hsu (ASP-DAC, 2011)

A 10 to 11.5GHz rotational phase and frequency detector for clock recovery circuit. - Fanta Chen; Min-Sheng Kao; Yu-Hao Hsu; Chih-Hsing Lin; Jen-Ming Wu; Ching-Te Chiu; Shuo-Hung Hsu (ISCAS, 2011)

An 8 × 8 20 Gbps Reconfigurable Load Balanced TDM Switch IC for High-Speed Networking. - Ching-Te Chiu; Yu-Hao Hsu; Jen-Ming Wu; Shuo-Hung Hsu; Min-Sheng Kao; Hou-Cheng Tzeng; Ming-Chang Du; Ping-Ling Yang; Ming-Hao Lu; Fanta Chen; Hung-Yu Lin; Yarsun Hsu (J. Signal Process. Syst., 2012)

Low Propagation Delay Load-Balanced 4 × 4 Switch Fabric IC in 0.13-µm CMOS Technology. - Ching-Te Chiu; Yu-Hao Hsu; Wei-Chih Lai; Jen-Ming Wu; Shawn S. H. Hsu; Yang-Syu Lin; Fanta Chen; Min-Sheng Kao; Yarsun Hsu (IEEE Trans. Very Large Scale Integr. Syst., 2013)

A 10-Gb/s Low Jitter Single-Loop Clock and Data Recovery Circuit With Rotational Phase Frequency Detector. - Fanta Chen; Min-Sheng Kao; Yu-Hao Hsu; Jen-Ming Wu; Ching-Te Chiu; Shawn S. H. Hsu; Mau-Chung Frank Chang (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)

20-Gb/s CMOS EA/MZ Modulator Driver With Intrinsic Parasitic Feedback Network. - Min-Sheng Kao; Fanta Chen; Yu-Hao Hsu; Jen-Ming Wu (IEEE Trans. Very Large Scale Integr. Syst., 2014)

Preventing Misuse of Duplicate Certificates in IoT/M2M Systems. - Yu-Hao Hsu; Fuchun Joseph Lin (ICCCN, 2017)

A 4nm 6163-TOPS/W/b $ mathbf{4790-TOPS/mm^{2}/b}$ SRAM Based Digital-Computing-in-Memory Macro Supporting Bit-Width Flexibility and Simultaneous MAC and Weight Update. - Haruki Mori; Wei-Chang Zhao; Cheng-En Lee; Chia-Fu Lee; Yu-Hao Hsu; Chao-Kai Chuang; Takeshi Hashizume; Hao-Chun Tung; Yao-Yi Liu; Shin-Rung Wu; Kerem Akarvardar; Tan-Li Chou; et al. (ISSCC, 2023)

A 3-nm 27.6-Mbit/mm2 Self-timed SRAM Enabling 0.48 - 1.2 V Wide Operating Range with Far-end Pre-charge and Weak-Bit Tracking. - Yumito Aoyagi; Makoto Yabuuchi; Tomotaka Tanaka; Yuichiro Ishii; Yoshiaki Osada; Takaaki Nakazato; Koji Nii; Isabel Wang; Yu-Hao Hsu; Hong-Chen Cheng; Hung-Jen Liao; Tsung-Yung Jonathan Chang (VLSI Technology and Circuits, 2023)

15.3 A 3nm FinFET 4.3GHz 21.1Mb/mm2 Double-Pumping 1-Read and 1-Write Pseudo-2-Port SRAM with Folded-Bitline Multi-Bank Architecture. - Masaru Haraguchi; Yorinobu Fujino; Yoshisato Yokoyama; Ming-Hung Chang; Yu-Hao Hsu; Hong-Chen Cheng; Koji Nii; Yih Wang; Tsung-Yung Jonathan Chang (ISSCC, 2024)

A 3.3GHz 1024X640 Multi-Bank Single-Port SRAM with Frequency Enhancing Techniques and 0.55V-1.35V Wide Voltage Range Operation in 3nm FinFET for HPC Applications. - Ming-Chieh Huang; Wei Wing Mar; Shankar Kanade; Boris Bai; Aditya Gayatri; Krishna Khairnar; Amy Lai; Yu-Hao Hsu; Hung-Jen Liao; Yih Wang; Tsung-Yung Jonathan Chang (VLSI Technology and Circuits, 2024)

Wideband 4-Port Patch Antenna Module Based Compact 8-Port Two-Module Antenna for 6G Upper Mid-Band 8 × 4 Device MIMO With Enhanced Spectral Efficiency. - Kin-Lu Wong; Yu-Hao Hsu; Cheng-Yu Lee; Wei-Yu Li (IEEE Access, 2024)

A 3-nm FinFET 27.6-Mbit/mm2 Single-Port 6T SRAM Enabling 0.48-1.2 V Wide Operating Range With Far-End Pre-Charge and Weak-Bit Tracking. - Yumito Aoyagi; Koji Nii; Makoto Yabuuchi; Tomotaka Tanaka; Yuichiro Ishii; Yoshiaki Osada; Takaaki Nakazato; Isabel Wang; Yu-Hao Hsu; Hong-Chen Cheng; Hung-Jen Liao; Tsung-Yung Jonathan Chang (IEEE J. Solid State Circuits, 2024)

A 3 nm-FinFET 4.3 GHz 21.1 Mb/mm2 Double-Pumping 1-Read and 1-Write Psuedo-2-Port SRAM With a Folded Bitline Multi-Bank Architecture. - Masaru Haraguchi; Yorinobu Fujino; Yoshisato Yokoyama; Ming-Hung Chang; Yu-Hao Hsu; Hong-Chen Cheng; Koji Nii; Yih Wang; Tsung-Yung Jonathan Chang (IEEE J. Solid State Circuits, 2025)