A 40 nm 0.32 V 3.5 MHz 11T single-ended bit-interleaving subthreshold SRAM with data-aware write-assist. - Yi-Wei Chiu; Yu-Hao Hu; Ming-Hsien Tu; Jun-Kai Zhao; Shyh-Jye Jou; Ching-Te Chuang (ISLPED, 2013)

40 nm Bit-Interleaving 12T Subthreshold SRAM With Data-Aware Write-Assist. - Yi-Wei Chiu; Yu-Hao Hu; Ming-Hsien Tu; Jun-Kai Zhao; Yuan-Hua Chu; Shyh-Jye Jou; Ching-Te Chuang (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)

A subthreshold SRAM with embedded data-aware write-assist and adaptive data-aware keeper. - Yi-Wei Chiu; Yu-Hao Hu; Jun-Kai Zhao; Shyh-Jye Jou; Ching-Te Chuang (ISCAS, 2016)