A 10Gbps, 1.24pJ/bit, burst-mode clock and data recovery with jitter suppression. - Ming-Chiuan Su; Wei-Zen Chen; Pei-Si Wu; Yu-Hsian Chen; Chao-Cheng Lee; Shyh-Jye Jou (CICC, 2013)

A 40nm 256kb 6T SRAM with threshold power-gating, low-swing global read bit-line, and charge-sharing write with Vtrip-tracking and negative source-line write-assists. - Chao-Kuei Chung; Chien-Yu Lu; Zhi-Hao Chang; Shyh-Jye Jou; Ching-Te Chuang; Ming-Hsien Tu; Yu-Hsian Chen; Yong-Jyun Hu; Paul-Sen Kan; Huan-Shun Huang; Kuen-Di Lee; Yung-Shin Kao (SoCC, 2014)

A 10-Gb/s, 1.24 pJ/bit, Burst-Mode Clock and Data Recovery With Jitter Suppression. - Ming-Chiuan Su; Wei-Zen Chen; Pei-Si Wu; Yu-Hsian Chen; Chao-Cheng Lee; Shyh-Jye Jou (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)