A Flexible and High-Performance Self-Organizing Feature Map Training Acceleration Circuit and Its Applications. - Yu-Hsiu Sun; Tzi-Dar Chiueh (AICAS, 2019)

Enabling Software-Defined RF Convergence with a Novel Coarse-Scale Heterogeneous Processor. - Daniel W. Bliss; Tutu Ajayi; Ali Akoglu; Ilkin Aliyev; Toygun Basaklar; Leul Belayneh; David T. Blaauw; John S. Brunhaver; Chaitali Chakrabarti; Liangliang Chang; Kuan-Yu Chen 001; Ming-Hung Chen; et al. (ISCAS, 2022)

A 507 GMACs/J 256-Core Domain Adaptive Systolic-Array-Processor for Wireless Communication and Linear-Algebra Kernels in 12nm FINFET. - Kuan-Yu Chen 001; Chi-Sheng Yang; Yu-Hsiu Sun; Chien-Wei Tseng; Morteza Fayazi; Xin He; Siying Feng; Yufan Yue; Trevor N. Mudge; Ronald G. Dreslinski; Hun-Seok Kim; David T. Blaauw (VLSI Technology and Circuits, 2022)

DAP: A 507-GMACs/J 256-Core Domain Adaptive Processor for Wireless Communication and Linear Algebra Kernels in 12-nm FINFET. - Kuan-Yu Chen 001; Chi-Sheng Yang; Yu-Hsiu Sun; Chien-Wei Tseng; Morteza Fayazi; Xin He; Siying Feng; Yufan Yue; Trevor N. Mudge; Ronald G. Dreslinski; Hun-Seok Kim; David T. Blaauw (IEEE J. Solid State Circuits, 2025)