Yu Hu

Proceedings of the IEEE Intelligent Vehicles Symposium, 2023

Generalized Few-shot Semantic Segmentation for LiDAR Point Clouds.

[BibT_eX]

[DOI]

IROS, 2023

Few-shot 3D LiDAR Semantic Segmentation for Autonomous Driving.

[BibT_eX]

[DOI]

Jilin Mei

Junbao Zhou

Proceedings of the IEEE International Conference on Robotics and Automation, 2023

Zero-shot Object Detection Based on Dynamic Semantic Vectors.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Robotics and Automation, 2023

Unleashing the Power of Gradient Signal-to-Noise Ratio for Zero-Shot NAS.

[BibT_eX]

[DOI]

Proceedings of the IEEE/CVF International Conference on Computer Vision, 2023

PA&DA: Jointly Sampling PAth and DAta for Consistent NAS.

[BibT_eX]

[DOI]

Proceedings of the IEEE/CVF Conference on Computer Vision and Pattern Recognition, 2023

PINAT: A Permutation INvariance Augmented Transformer for NAS Predictor.

[BibT_eX]

[DOI]

Proceedings of the Thirty-Seventh AAAI Conference on Artificial Intelligence, 2023

2022

STC-NAS: Fast neural architecture search with source-target consistency.

[BibT_eX]

[DOI]

Neurocomputing, 2022

SMS-MPC: Adversarial Learning-based Simultaneous Prediction Control with Single Model for Mobile Robots.

[BibT_eX]

[DOI]

Andong Yang

Wei Li

Proceedings of the IEEE/RSJ International Conference on Intelligent Robots and Systems, 2022

Closing the Dynamics Gap via Adversarial and Reinforcement Learning for High-Speed Racing.

[BibT_eX]

[DOI]

Proceedings of the International Joint Conference on Neural Networks, 2022

Searching for BurgerFormer with Micro-Meso-Macro Space Design.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Machine Learning, 2022

AGNAS: Attention-Guided Micro and Macro-Architecture Search.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Machine Learning, 2022

Repeatable Pattern Mining for Accurate Subtraction of Backgrounds with Waving Objects in Underwater Videos.

[BibT_eX]

[DOI]

Proceedings of the 9th IEEE International Conference on Data Science and Advanced Analytics, 2022

2021

Happy Emotion Recognition From Unconstrained Videos Using 3D Hybrid Deep Features.

[BibT_eX]

[DOI]

IEEE Access, 2021

KFS-LIO: Key-Feature Selection for Lightweight Lidar Inertial Odometry.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Robotics and Automation, 2021

DU-DARTS: Decreasing the Uncertainty of Differentiable Architecture Search.

[BibT_eX]

[DOI]

Proceedings of the 32nd British Machine Vision Conference 2021, 2021

DDSAS: Dynamic and Differentiable Space-Architecture Search.

[BibT_eX]

[DOI]

Proceedings of the Asian Conference on Machine Learning, 2021

2020

INOR - An Intelligent noise reduction method to defend against adversarial audio examples.

[BibT_eX]

[DOI]

Neurocomputing, 2020

MultiPAD: A Multivariant Partition-Based Method for Audio Adversarial Examples Detection.

[BibT_eX]

[DOI]

IEEE Access, 2020

Sequence Triggered Hardware Trojan in Neural Network Accelerator.

[BibT_eX]

[DOI]

Proceedings of the 38th IEEE VLSI Test Symposium, 2020

Two-Stage Safe Reinforcement Learning for High-Speed Autonomous Racing.

[BibT_eX]

[DOI]

Proceedings of the 2020 IEEE International Conference on Systems, Man, and Cybernetics, 2020

Lightdet: A Lightweight and Accurate Object Detection Network.

[BibT_eX]

[DOI]

Proceedings of the 2020 IEEE International Conference on Acoustics, 2020

Prediction Stability: A New Metric for Quantitatively Evaluating DNN Outputs.

[BibT_eX]

[DOI]

Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020

Exploring Spatial-Temporal Multi-Frequency Analysis for High-Fidelity and Temporal-Consistency Video Prediction.

[BibT_eX]

[DOI]

Proceedings of the 2020 IEEE/CVF Conference on Computer Vision and Pattern Recognition, 2020

Survey: Hardware Trojan Detection for Netlist.

[BibT_eX]

[DOI]

Proceedings of the 29th IEEE Asian Test Symposium, 2020

2019

PUFPass: A password management mechanism based on software/hardware codesign.

[BibT_eX]

[DOI]

Integr., 2019

PosNeg-Balanced Anchors with Aligned Features for Single-Shot Object Detection.

[BibT_eX]

[DOI]

CoRR, 2019

Scan Chain Based Attacks and Countermeasures: A Survey.

[BibT_eX]

[DOI]

IEEE Access, 2019

Implementation of Parametric Hardware Trojan in FPGA.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Test Conference in Asia, 2019

2018

Deterministic and Probabilistic Diagnostic Challenge Generation for Arbiter Physical Unclonable Function.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

RT3D: Real-Time 3-D Vehicle Detection in LiDAR Point Cloud for Autonomous Driving.

[BibT_eX]

[DOI]

IEEE Robotics Autom. Lett., 2018

Modeling attacks on strong physical unclonable functions strengthened by random number and weak PUF.

[BibT_eX]

[DOI]

Proceedings of the 36th IEEE VLSI Test Symposium, 2018

See and Think: Disentangling Semantic Scene Completion.

[BibT_eX]

[DOI]

Proceedings of the Advances in Neural Information Processing Systems 31: Annual Conference on Neural Information Processing Systems 2018, 2018

Grey Zone in Pre-Silicon Hardware Trojan Detection.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Test Conference in Asia, 2018

VarNet: Exploring Variations for Unsupervised Video Prediction.

[BibT_eX]

[DOI]

Proceedings of the 2018 IEEE/RSJ International Conference on Intelligent Robots and Systems, 2018

Hardware Trojan in FPGA CNN Accelerator.

[BibT_eX]

[DOI]

Proceedings of the 27th IEEE Asian Test Symposium, 2018

PUF Based Pay-Per-Device Scheme for IP Protection of CNN Model.

[BibT_eX]

[DOI]

Proceedings of the 27th IEEE Asian Test Symposium, 2018

Bias PUF based Secure Scan Chain Design.

[BibT_eX]

[DOI]

Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2018

2017

Going Cooler With Timing-Constrained TeSHoP: A Temperature Sensing-Based Hotspot-Driven Placement Technique for FPGAs.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2017

Power-Utility-Driven Write Management for MLC PCM.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2017

LAPS: Layout-Aware Path Selection for Post-Silicon Timing Characterization.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2017

GeoCueDepth: Exploiting geometric structure cues to estimate depth from a single image.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE/RSJ International Conference on Intelligent Robots and Systems, 2017

VPUF: Voter based physical unclonable function with high reliability and modeling attack resistance.

[BibT_eX]

[DOI]

Proceedings of the 23rd IEEE International Symposium on On-Line Testing and Robust System Design, 2017

Leveraging FVT-margins in design space exploration for FFGA-based CNN accelerators.

[BibT_eX]

[DOI]

Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017

Fault diagnosis of arbiter physical unclonable function.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Polymorphic PUF: Exploiting reconfigurability of CPU+FPGA SoC to resist modeling attack.

[BibT_eX]

[DOI]

Proceedings of the 2017 Asian Hardware Oriented Security and Trust Symposium, 2017

2016

TSocket: Thermal Sustainable Power Budgeting.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2016

RPUF: Physical Unclonable Function with Randomized Challenge to resist modeling attack.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE Asian Hardware-Oriented Security and Trust, 2016

TeSHoP: A Temperature Sensing based Hotspot-Driven Placement technique for FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016

DCPUF: Placement and Routing Constraint based Dynamically Configured Physical Unclonable Function on FPGA (Abstact Only).

[BibT_eX]

[DOI]

Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2016

POSTER: Attack on Non-Linear Physical Unclonable Function.

[BibT_eX]

[DOI]

Proceedings of the 2016 ACM SIGSAC Conference on Computer and Communications Security, 2016

Efficient Attack on Non-linear Current Mirror PUF with Genetic Algorithm.

[BibT_eX]

[DOI]

Proceedings of the 25th IEEE Asian Test Symposium, 2016

2015

Diagnosis and Layout Aware (DLA) Scan Chain Stitching.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2015

OPUF: Obfuscation logic based physical unclonable function.

[BibT_eX]

[DOI]

Proceedings of the 21st IEEE International On-Line Testing Symposium, 2015

Impact assessment of net metering on smart home cyberattack detection.

[BibT_eX]

[DOI]

Proceedings of the 52nd Annual Design Automation Conference, 2015

2014

Diagnose Failures Caused by Multiple Locations at a Time.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2014

Reliability-Oriented Placement and Routing Algorithm for SRAM-Based FPGAs.

[BibT_eX]

[DOI]

Keheng Huang

IEEE Trans. Very Large Scale Integr. Syst., 2014

Orchestrator: Guarding Against Voltage Emergencies in Multithreaded Applications.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2014

Short-SET: An energy-efficient write scheme for MLC PCM.

[BibT_eX]

[DOI]

Bing Li

Proceedings of the IEEE Non-Volatile Memory Systems and Applications Symposium, 2014

Partial-SET: Write speedup of PCM main memory.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Thermal-Sustainable Power Budgeting for Dynamic Threading.

[BibT_eX]

[DOI]

Proceedings of the 51st Annual Design Automation Conference 2014, 2014

SwimmingLane: A composite approach to mitigate voltage droop effects in 3D power delivery network.

[BibT_eX]

[DOI]

Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013

Tolerating Noise in MLC PCM with Multi-Bit Error Correction Code.

[BibT_eX]

[DOI]

Proceedings of the IEEE 19th Pacific Rim International Symposium on Dependable Computing, 2013

HHC: Hierarchical hardware checkpointing to accelerate fault recovery for SRAM-based FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 2013

Capturing post-silicon variation by layout-aware path-delay testing.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2013

Orchestrator: a low-cost solution to reduce voltage emergencies for multi-threaded applications.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2013

2012

IVF: Characterizing the Vulnerability of Microprocessor Structures to Intermittent Faults.

[BibT_eX]

[DOI]

Songjun Pan

IEEE Trans. Very Large Scale Integr. Syst., 2012

Off-path leakage power aware routing for SRAM-based FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

In-Field Testing of NAND Flash Storage: Why and How?

[BibT_eX]

[DOI]

Xinli Gu

Proceedings of the 21st IEEE Asian Test Symposium, 2012

2011

Using Launch-on-Capture for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

Capture-power-aware test data compression using selective encoding.

[BibT_eX]

[DOI]

Integr., 2011

Oware: Operand width Aware Redundant Execution for Whole-Processor Error Detection.

[BibT_eX]

[DOI]

Zhongliang Chen

Intell. Autom. Soft Comput., 2011

Scan chain design for shift power reduction in scan-based testing.

[BibT_eX]

[DOI]

Jia Li

Sci. China Inf. Sci., 2011

Transparent dynamic binding with fault-tolerant cache coherence protocol for chip multiprocessors.

[BibT_eX]

[DOI]

Shuchang Shan

Proceedings of the 2011 IEEE/IFIP International Conference on Dependable Systems and Networks, 2011

On diagnosis of multiple faults using compacted responses.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2011

A cost-effective substantial-impact-filter based method to tolerate voltage emergencies.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2011

Cross-layer optimized placement and routing for FPGA soft error mitigation.

[BibT_eX]

[DOI]

Keheng Huang

Proceedings of the Design, Automation and Test in Europe, 2011

Exploiting Free LUT Entries to Mitigate Soft Errors in SRAM-based FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 20th IEEE Asian Test Symposium, 2011

2010

X-Filling for Simultaneous Shift- and Capture-Power Reduction in At-Speed Scan-Based Testing.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2010

Diagnosis of multiple arbitrary faults with mask and reinforcement effect.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2010

Substantial Fault Pair At-a-Time (SFPAT): An Automatic Diagnostic Pattern Generation Method.

[BibT_eX]

[DOI]

Proceedings of the 19th IEEE Asian Test Symposium, 2010

2009

Online Computing and Predicting Architectural Vulnerability Factor of Microprocessor Structures.

[BibT_eX]

[DOI]

Songjun Pan

Proceedings of the 2009 15th IEEE Pacific Rim International Symposium on Dependable Computing, 2009

2008

Design-for-Testability Features and Test Implementation of a Giga Hertz General Purpose Microprocessor.

[BibT_eX]

[DOI]

J. Comput. Sci. Technol., 2008

Codeword Selection for Crosstalk Avoidance and Error Correction on Interconnects.

[BibT_eX]

[DOI]

Proceedings of the 26th IEEE VLSI Test Symposium (VTS 2008), April 27, 2008

Diagnosis of Mask-Effect Multiple Timing Faults in Scan Chains.

[BibT_eX]

[DOI]

Proceedings of the 2008 IEEE International Test Conference, 2008

Deterministic Diagnostic Pattern Generation (DDPG) for Compound Defects.

[BibT_eX]

[DOI]

Proceedings of the 2008 IEEE International Test Conference, 2008

On capture power-aware test data compression for scan-based testing.

[BibT_eX]

[DOI]

Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

A Case Study on At-Speed Testing for a Gigahertz Microprocessor.

[BibT_eX]

[DOI]

Proceedings of the 4th IEEE International Symposium on Electronic Design, 2008

Adaptive Diagnostic Pattern Generation for Scan Chains.

[BibT_eX]

[DOI]

Fei Wang

Proceedings of the 4th IEEE International Symposium on Electronic Design, 2008

A Scan-Based Delay Test Method for Reduction of Overtesting.

[BibT_eX]

[DOI]

Proceedings of the 4th IEEE International Symposium on Electronic Design, 2008

Channel Width Utilization Improvement in Testing NoC-Based Systems for Test Time Reduction.

[BibT_eX]

[DOI]

Proceedings of the 4th IEEE International Symposium on Electronic Design, 2008

iFill: An Impact-Oriented X-Filling Method for Shift- and Capture-Power Reduction in At-Speed Scan-Based Testing.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2008

Observation Point Oriented Deterministic Diagnosis Pattern Generation (DDPG) for Chain Diagnosis.

[BibT_eX]

[DOI]

Proceedings of the 17th IEEE Asian Test Symposium, 2008

A design- for-diagnosis technique for diagnosing both scan chain faults and combinational circuit faults.

[BibT_eX]

[DOI]

Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

On reducing both shift and capture power for scan-based testing.

[BibT_eX]

[DOI]

Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

Localized random access scan: Towards low area and routing overhead.

[BibT_eX]

[DOI]

Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

Robust test generation for power supply noise induced path delay faults.

[BibT_eX]

[DOI]

Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

2007

Embedded Test Decompressor to Reduce the Required Channels and Vector Memory of Tester for Complex Processor Circuit.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2007

Leakage Current Optimization Techniques During Test Based on Don't Care Bits Assignment.

[BibT_eX]

[DOI]

J. Comput. Sci. Technol., 2007

The design-for-testability features of a general purpose microprocessor.

[BibT_eX]

[DOI]

Proceedings of the 2007 IEEE International Test Conference, 2007

An On-Chip Test Clock Control Scheme for Multi-Clock At-Speed Testing.

[BibT_eX]

[DOI]

Xiaoxin Fan

Laung-Terng Wang

Proceedings of the 16th Asian Test Symposium, 2007

2006

Compression/Scan Co-design for Reducing Test Data Volume, Scan-in Power Dissipation, and Test Application Time.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2006

An on-chip combinational decompressor for reducing test data volume.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

A Scan Chain Adjustment Technology for Test Power Reduction.

[BibT_eX]

[DOI]

Jia Li

Proceedings of the 15th Asian Test Symposium, 2006

Test data compression based on clustered random access scan.

[BibT_eX]

[DOI]

Proceedings of the 15th Asian Test Symposium, 2006

2005

Wrapper Scan Chains Design for Rapid and Low Power Testing of Embedded Cores.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2005

Compression/Scan Co-Design for Reducing Test Data Volume, Scan-in Power Dissipation and Test Application Time.

[BibT_eX]

[DOI]

Proceedings of the 11th IEEE Pacific Rim International Symposium on Dependable Computing (PRDC 2005), 2005

Using MUXs Network to Hide Bunches of Scan Chains.

[BibT_eX]

[DOI]

Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

Scan Data Volume Reduction Using Periodically Alterable MUXs Decompressor.

[BibT_eX]

[DOI]

Yinhe Han

Shivakumar Swaminathan