Via-Aware Global Routing for Good VLSI Manufacturability and High Yield. - Yang Yang 040; Tong Jing; Xianlong Hong; Yu Hu 002; Qi Zhu 002; Xiaodong Hu 001; Guiying Yan (ASAP, 2005)

An-OARSMan: obstacle-avoiding routing tree construction with good length performance. - Yu Hu 002; Tong Jing; Xianlong Hong; Zhe Feng 002; Xiaodong Hu 001; Guiying Yan (ASP-DAC, 2005)

A Routing Paradigm with Novel Resources Estimation and Routability Models for X-Architecture Based Physical Design. - Yu Hu 002; Tong Jing; Xianlong Hong; Xiaodong Hu 001; Guiying Yan (SAMOS, 2005)

DraXRouter: global routing in X-Architecture with dynamic resource assignment. - Zhen Cao; Tong Jing; Yu Hu 002; Yiyu Shi 001; Xianlong Hong; Xiaodong Hu 001; Guiying Yan (ASP-DAC, 2006)

Simultaneous time slack budgeting and retiming for dual-Vdd FPGA power reduction. - Yu Hu 002; Yan Lin 001; Lei He 001; Tim Tuan (DAC, 2006)

An efficient chip-level time slack allocation algorithm for Dual-Vdd FPGA power reduction. - Yan Lin 001; Yu Hu 002; Lei He 001; Vijay Raghunat (ISLPED, 2006)

An O(nlogn) algorithm for obstacle-avoiding routing tree construction in the lambda-geometry plane. - Zhe Feng 002; Yu Hu 002; Tong Jing; Xianlong Hong; Xiaodong Hu 001; Guiying Yan (ISPD, 2006)

ACO-Steiner: Ant Colony Optimization Based Rectilinear Steiner Minimal Tree Algorithm. - Yu Hu 002; Tong Jing; Zhe Feng 002; Xianlong Hong; Xiaodong Hu 001; Guiying Yan (J. Comput. Sci. Technol., 2006)

DpRouter: A Fast and Accurate Dynamic-Pattern-Based Global Routing Algorithm. - Zhen Cao; Tong Jing; Jinjun Xiong; Yu Hu 002; Lei He 001; Xianlong Hong (ASP-DAC, 2007)

Design, synthesis and evaluation of heterogeneous FPGA with mixed LUTs and macro-gates. - Yu Hu 002; Satyaki Das; Steven Trimberger; Lei He 001 (ICCAD, 2007)

Exploiting symmetry in SAT-based Boolean matching for heterogeneous FPGA technology mapping. - Yu Hu 002; Victor Shih; Rupak Majumdar; Lei He 001 (ICCAD, 2007)

Minimal skew clock embedding considering time variant temperature gradient. - Hao Yu 001; Yu Hu 002; Chunchen Liu; Lei He 001 (ISPD, 2007)

Fast dual-vdd buffering based on interconnect prediction and sampling. - Yu Hu 002; King Ho Tam; Tong Jing; Lei He 001 (SLIP, 2007)

lambda-OAT: lambda-Geometry Obstacle-Avoiding Tree Construction With O(nlog n) Complexity. - Tom Tong Jing; Zhe Feng 002; Yu Hu 002; Xianlong Hong; Xiaodong Hu 001; Guiying Yan (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

FPGA area reduction by multi-output function based sequential resynthesis. - Yu Hu 002; Victor Shih; Rupak Majumdar; Lei He 001 (DAC, 2008)

Robust FPGA resynthesis based on fault-tolerant Boolean matching. - Yu Hu 002; Zhe Feng 002; Lei He 001; Rupak Majumdar (ICCAD, 2008)

A full-scale solution to the rectilinear obstacle-avoiding Steiner problem. - Tom Tong Jing; Yu Hu 002; Zhe Feng 002; Xianlong Hong; Xiaodong Hu 001; Guiying Yan (Integr., 2008)

Fashion: A Fast and Accurate Solution to Global Routing Problem. - Zhen Cao; Tong Jing; Jinjun Xiong; Yu Hu 002; Zhe Feng 002; Lei He 001; Xianlong Hong (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

Exploiting Symmetries to Speed Up SAT-Based Boolean Matching for Logic Synthesis of FPGAs. - Yu Hu 002; Victor Shih; Rupak Majumdar; Lei He 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

Dual-Vdd Buffer Insertion for Power Reduction. - King Ho Tam; Yu Hu 002; Lei He 001; Tom Tong Jing; Xinyi Zhang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

Physical synthesis for FPGA interconnect power reduction by dual-Vdd budgeting and retiming. - Yu Hu 002; Yan Lin 001; Lei He 001; Tim Tuan (ACM Trans. Design Autom. Electr. Syst., 2008)

IPR: In-Place Reconfiguration for FPGA fault tolerance. - Zhe Feng 002; Yu Hu 002; Lei He 001; Rupak Majumdar (ICCAD, 2009)

Simultaneous test pattern compaction, ordering and X-filling for testing power reduction. - Ju-Yueh Lee; Yu Hu 002; Rupak Majumdar; Lei He 001 (ISQED, 2009)

Worst case timing jitter and amplitude noise in differential signaling. - Wei Yao 002; Yiyu Shi 001; Lei He 001; Sudhakar Pamarti; Yu Hu 002 (ISQED, 2009)

Design and Synthesis of Programmable Logic Block With Mixed LUT and Macrogate. - Yu Hu 002; Satyaki Das; Steven Trimberger; Lei He 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009)

Fault-tolerant resynthesis with dual-output LUTs. - Ju-Yueh Lee; Yu Hu 002; Rupak Majumdar; Lei He 001; Minming Li (ASP-DAC, 2010)

Rewiring for robustness. - Manu Jose; Yu Hu 002; Rupak Majumdar; Lei He 001 (DAC, 2010)

RALF: Reliability Analysis for Logic Faults - An exact algorithm and its applications. - Samuel B. Luckenbill; Ju-Yueh Lee; Yu Hu 002; Rupak Majumdar; Lei He 001 (DATE, 2010)

Building a faster boolean matcher using bloom filter. - Chun Zhang; Yu Hu 002; Lingli Wang; Lei He 001; Jiarong Tong (FPGA, 2010)

Accelerating FPGA design space exploration using circuit similarity-based placement. - Xiaoyu Shi; Dahua Zeng; Yu Hu 002; Guohui Lin; Osmar R. Zaïane (FPT, 2010)

On power and fault-tolerance optimization in FPGA physical synthesis. - Manu Jose; Yu Hu 002; Rupak Majumdar (ICCAD, 2010)

Engineering a scalable Boolean matching based on EDA SaaS 2.0. - Chun Zhang; Yu Hu 002; Lingli Wang; Lei He 001; Jiarong Tong (ICCAD, 2010)

Accelerating Boolean Matching Using Bloom Filter. - Chun Zhang; Yu Hu 002; Lingli Wang; Lei He 001; Jiarong Tong (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010)

A method to build reconfigurable architectures by extracting common subgraphs. - Tianyun Zhang; Rui Zhang; Lingli Wang; Yu Hu 002 (ASICON, 2011)

Acceleration of Multi-agent Simulation on FPGAs. - Lintao Cui; Jing Chen; Yu Hu 002; Jinjun Xiong; Zhe Feng 002; Lei He 001 (FPL, 2011)

IPF: In-Place X-Filling to Mitigate Soft Errors in SRAM-Based FPGAs. - Zhe Feng 002; Naifeng Jing; GengSheng Chen; Yu Hu 002; Lei He 001 (FPL, 2011)

Enhancement of incremental design for FPGAs using circuit similarity. - Xiaoyu Shi; Dahua Zeng; Yu Hu 002; Guohui Lin; Osmar R. Zaïane (ISQED, 2011)

System-in-Package: Electrical and Layout Perspectives. - Lei He 001; Shauki Elassaad; Yiyu Shi 001; Yu Hu 002; Wei Yao 002 (Found. Trends Electron. Des. Autom., 2011)

In-Place FPGA Retiming for Mitigation of Variational Single-Event Transient Faults. - Wenyao Xu; Jia Wang; Yu Hu 002; Ju-Yueh Lee; Fang Gong; Lei He 001; Majid Sarrafzadeh (IEEE Trans. Circuits Syst. I Regul. Pap., 2011)

A Simulation Study of Connected Vehicle Systems Using Named Data Networking. - Tao Jiang; Xiaowei Xu 004; Lu Pu; Yu Hu 002; Zhijun Qiu (CloudComp, 2013)

An energy-efficient sub-Nyquist sampling method based on compressed sensing in wireless sensor network for vehicle detection. - Jiangchen Li; Xiaowei Xu 004; Hongpeng Zhao; Yu Hu 002; Tony Z. Qiu (ICCVE, 2013)

Fast Filter-Based Boolean Matchers. - Chaofan Yu; Lingli Wang; Chun Zhang; Yu Hu 002; Lei He 001 (IEEE Embed. Syst. Lett., 2013)

SPECO: Stochastic Perturbation based Clock tree Optimization considering temperature uncertainty. - Sina Basir-Kazeruni; Hao Yu 001; Fang Gong; Yu Hu 002; Chunchen Liu; Lei He 001 (Integr., 2013)

On-bed sleep posture recognition based on body-earth mover's distance. - Xiaowei Xu 004; Feng Lin 004; Aosen Wang; Chen Song 001; Yu Hu 002; Wenyao Xu (BioCAS, 2015)

Energy-efficient pipelined DTW architecture on hybrid embedded platforms. - Hanqing Zhou; Xiaowei Xu 004; Yu Hu 002; Guangyu Yu; Zeyu Yan; Feng Lin 004; Wenyao Xu (IGSC, 2015)

A flexible control study of variable speed limit in connected vehicle systems. - Lu Pu; Xiaowei Xu 004; Han He; Hanqing Zhou; Zhijun Qiu; Yu Hu 002 (Int. J. Embed. Syst., 2015)

Body-Earth Mover's Distance: A Matching-Based Approach for Sleep Posture Recognition. - Xiaowei Xu 004; Feng Lin 004; Aosen Wang; Yu Hu 002; Ming-Chun Huang; Wenyao Xu (IEEE Trans. Biomed. Circuits Syst., 2016)

An Efficient Memristor-based Distance Accelerator for Time Series Data Mining on Data Centers. - Xiaowei Xu 004; Dewen Zeng; Wenyao Xu; Yiyu Shi 001; Yu Hu 002 (DAC, 2017)

Efficient hardware implementation of cellular neural networks with powers-of-two based incremental quantization. - Xiaowei Xu 004; Qing Lu 001; Tianchen Wang; Jinglan Liu; Yu Hu 002; Yiyu Shi 001 (NCS, 2017)

Quantization of Fully Convolutional Networks for Accurate Biomedical Image Segmentation. - Xiaowei Xu 004; Qing Lu 001; Lin Yang 003; Xiaobo Sharon Hu; Danny Z. Chen; Yu Hu 002; Yiyu Shi 001 (CVPR, 2018)

Scalable and Parameterized Architecture for Efficient Stream Mining. - Li Zhang 021; Dawei Li 012; Xuecheng Zou; Yu Hu 002; Xiaowei Xu 004 (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2018)

Efficient Hardware Implementation of Cellular Neural Networks with Incremental Quantization and Early Exit. - Xiaowei Xu 004; Qing Lu 001; Tianchen Wang; Yu Hu 002; Chen Zhuo; Jinglan Liu; Yiyu Shi 001 (ACM J. Emerg. Technol. Comput. Syst., 2018)

Accelerating Dynamic Time Warping With Memristor-Based Customized Fabrics. - Xiaowei Xu 004; Feng Lin 004; Aosen Wang; Xinwei Yao 001; Qing Lu 001; Wenyao Xu; Yiyu Shi 001; Yu Hu 002 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

MDA: A Reconfigurable Memristor-Based Distance Accelerator for Time Series Mining on Data Centers. - Xiaowei Xu 004; Feng Lin 004; Wenyao Xu; Xinwei Yao 001; Yiyu Shi 001; Dewen Zeng; Yu Hu 002 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019)

Quantization of Deep Neural Networks for Accurate EdgeComputing. - Wentao Chen; Hailong Qiu; Jian Zhuang; Chutong Zhang; Yu Hu 002; Qing Lu 001; Tianchen Wang; Yiyu Shi 001; Meiping Huang; Xiaowei Xu 004 (CoRR, 2021)

Quantization of Deep Neural Networks for Accurate Edge Computing. - Wentao Chen; Hailong Qiu; Jian Zhuang; Chutong Zhang; Yu Hu 002; Qing Lu 001; Tianchen Wang; Yiyu Shi 001; Meiping Huang; Xiaowei Xu 004 (ACM J. Emerg. Technol. Comput. Syst., 2021)