Yu Huang

Orcid: 0000-0003-2619-4686

Affiliations:

Mentor Graphics Corporation, Wilsonville, OR, USA
University of Iowa, IA, USA (former)

According to our database¹, Yu Huang authored at least 80 papers between 2000 and 2021.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

Timeline

Legend:

Book

In proceedings

Article

PhD thesis

Dataset

Other

Bibliography

2021

Special Session - Test for AI Chips: from DFT to On-line Testing.

[BibT_eX]

[DOI]

Proceedings of the 39th IEEE VLSI Test Symposium, 2021

Automotive Test and Reliability.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Test Conference in Asia, 2021

Diagnosis and Yield Learning.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Test Conference in Asia, 2021

2020

Low Cost Hypercompression of Test Data.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Diagnosis of Intermittent Scan Chain Faults Through a Multistage Neural Network Reasoning Process.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Effective Design of Layout-Friendly EDT Decompressor.

[BibT_eX]

[DOI]

Proceedings of the 38th IEEE VLSI Test Symposium, 2020

Prediction of Test Pattern Count and Test Data Volume for Scan Architectures under Different Input Channel Configurations.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Test Conference, 2020

Fast Bring-Up of an AI SoC through IEEE 1687 Integrating Embedded TAPs and IEEE 1500 Interfaces.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Test Conference, 2020

Estimation of Test Data Volume for Scan Architectures with Different Numbers of Input Channels.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Test Conference in Asia, 2020

Efficient Prognostication of Pattern Count with Different Input Compression Ratios.

[BibT_eX]

[DOI]

Proceedings of the IEEE European Test Symposium, 2020

2019

Innovative Practices on DFT for AI Chips.

[BibT_eX]

[DOI]

Proceedings of the 37th IEEE VLSI Test Symposium, 2019

Reversible Scan Based Diagnostic Patterns.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on VLSI Design, Automation and Test, 2019

Tutorial 1B: AI Chip Technologies and DFT Methodologies.

[BibT_eX]

[DOI]

Yu Huang

Rahul Singhal

Proceedings of the 32nd IEEE International System-on-Chip Conference, 2019

A Case Study of Testing Strategy for AI SoC.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Test Conference in Asia, 2019

Non-Adaptive Pattern Reordering to Improve Scan Chain Diagnostic Resolution.

[BibT_eX]

[DOI]

Yu Huang

Jakub Janicki

Szczepan Urban

Proceedings of the 24th IEEE European Test Symposium, 2019

Deep Learning Based Test Compression Analyzer.

[BibT_eX]

[DOI]

Proceedings of the 28th IEEE Asian Test Symposium, 2019

Improving scan chain diagnostic accuracy using multi-stage artificial neural networks.

[BibT_eX]

[DOI]

Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

2018

Innovative practices on machine learning for emerging applications.

[BibT_eX]

[DOI]

Proceedings of the 36th IEEE VLSI Test Symposium, 2018

Special session on machine learning for test and diagnosis.

[BibT_eX]

[DOI]

Krishnendu Chakrabarty

Li-C. Wang

Gaurav Veda

Yu Huang

Proceedings of the 36th IEEE VLSI Test Symposium, 2018

Hypercompression of Test Patterns.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Test Conference, 2018

Industrial Case Studies of SoC Test Scheduling Optimization by Selecting Appropriate EDT Architectures.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Test Conference in Asia, 2018

2017

On designing two-dimensional scan architecture for test chips.

[BibT_eX]

[DOI]

Yu Huang

Wu-Tung Cheng

Proceedings of the 2017 International Symposium on VLSI Design, Automation and Test, 2017

Scan Chain Diagnosis Based on Unsupervised Machine Learning.

[BibT_eX]

[DOI]

Proceedings of the 26th IEEE Asian Test Symposium, 2017

2015

Diagnosis and Layout Aware (DLA) Scan Chain Stitching.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2015

Scan Test Bandwidth Management for Ultralarge-Scale System-on-Chip Architectures.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2015

Hybrid Hierarchical and Modular Tests for SoC Designs.

[BibT_eX]

[DOI]

Proceedings of the 24th IEEE North Atlantic Test Workshop, 2015

Advancements in diagnosis driven yield analysis (DDYA): A survey of state-of-the-art scan diagnosis and yield analysis technologies.

[BibT_eX]

[DOI]

Yu Huang

Wu Yang

Wu-Tung Cheng

Proceedings of the 20th IEEE European Test Symposium, 2015

2014

Diagnose Failures Caused by Multiple Locations at a Time.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2014

Test Compression Improvement with EDT Channel Sharing in SoC Designs.

[BibT_eX]

[DOI]

Proceedings of the IEEE 23rd North Atlantic Test Workshop, 2014

Bit selection algorithm suitable for high-volume production of SRAM-PUF.

[BibT_eX]

[DOI]

Proceedings of the 2014 IEEE International Symposium on Hardware-Oriented Security and Trust, 2014

2013

Distributed dynamic partitioning based diagnosis of scan chain.

[BibT_eX]

[DOI]

Proceedings of the 31st IEEE VLSI Test Symposium, 2013

EDT bandwidth management - Practical scenarios for large SoC designs.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International Test Conference, 2013

2012

Improved volume diagnosis throughput using dynamic design partitioning.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Test Conference, 2012

A Hybrid Flow for Memory Failure Bitmap Classification.

[BibT_eX]

[DOI]

Proceedings of the 21st IEEE Asian Test Symposium, 2012

2010

On Reducing Scan Shift Activity at RTL.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

Test cycle power optimization for scan-based designs.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE International Test Conference, 2010

Case study of scan chain diagnosis and PFA on a low yield wafer.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE International Test Conference, 2010

Full-circuit SPICE simulation based validation of dynamic delay estimation.

[BibT_eX]

[DOI]

Proceedings of the 15th European Test Symposium, 2010

Enhance Profiling-Based Scan Chain Diagnosis by Pattern Masking.

[BibT_eX]

[DOI]

Wu-Tung Cheng

Yu Huang

Proceedings of the 19th IEEE Asian Test Symposium, 2010

Emulating and diagnosing IR-drop by using dynamic SDF.

[BibT_eX]

[DOI]

Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2009

On Improving Diagnostic Test Generation for Scan Chain Failures.

[BibT_eX]

[DOI]

Proceedings of the Eighteentgh Asian Test Symposium, 2009

Scan Chain Diagnosis by Adaptive Signal Profiling with Manufacturing ATPG Patterns.

[BibT_eX]

[DOI]

Proceedings of the Eighteentgh Asian Test Symposium, 2009

2008

Scan Shift Power Reduction by Freezing Power Sensitive Scan Cells.

[BibT_eX]

[DOI]

Xijiang Lin

Yu Huang

J. Electron. Test., 2008

Survey of Scan Chain Diagnosis.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 2008

Reducing Scan Shift Power at RTL.

[BibT_eX]

[DOI]

Proceedings of the 26th IEEE VLSI Test Symposium (VTS 2008), April 27, 2008

Deterministic Diagnostic Pattern Generation (DDPG) for Compound Defects.

[BibT_eX]

[DOI]

Proceedings of the 2008 IEEE International Test Conference, 2008

Detection and Diagnosis of Static Scan Cell Internal Defect.

[BibT_eX]

[DOI]

Proceedings of the 2008 IEEE International Test Conference, 2008

Diagnose Multiple Stuck-at Scan Chain Faults.

[BibT_eX]

[DOI]

Yu Huang

Wu-Tung Cheng

Ruifeng Guo

Proceedings of the 13th European Test Symposium, 2008

Observation Point Oriented Deterministic Diagnosis Pattern Generation (DDPG) for Chain Diagnosis.

[BibT_eX]

[DOI]

Proceedings of the 17th IEEE Asian Test Symposium, 2008

2007

Effects of Embedded Decompression and Compaction Architectures on Side-Channel Attack Resistance.

[BibT_eX]

[DOI]

Chunsheng Liu

Yu Huang

Proceedings of the 25th IEEE VLSI Test Symposium (VTS 2007), 2007

Diagnose compound scan chain and system logic defects.

[BibT_eX]

[DOI]

Proceedings of the 2007 IEEE International Test Conference, 2007

A complete test set to diagnose scan chain failures.

[BibT_eX]

[DOI]

Ruifeng Guo

Yu Huang

Wu-Tung Cheng

Proceedings of the 2007 IEEE International Test Conference, 2007

Dynamic learning based scan chain diagnosis.

[BibT_eX]

[DOI]

Yu Huang

Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

Scan Diagnosis and Its Successful Industrial Applications.

[BibT_eX]

[DOI]

Proceedings of the 16th Asian Test Symposium, 2007

Effect of IR-Drop on Path Delay Testing Using Statistical Analysis.

[BibT_eX]

[DOI]

Chunsheng Liu

Yang Wu

Yu Huang

Proceedings of the 16th Asian Test Symposium, 2007

A RTL Testability Analyzer Based on Logical Virtual Prototyping.

[BibT_eX]

[DOI]

Proceedings of the 16th Asian Test Symposium, 2007

Programmable Logic BIST for At-speed Test.

[BibT_eX]

[DOI]

Yu Huang

Xijiang Lin

Proceedings of the 16th Asian Test Symposium, 2007

Fault Dictionary Based Scan Chain Failure Diagnosis.

[BibT_eX]

[DOI]

Ruifeng Guo

Yu Huang

Wu-Tung Cheng

Proceedings of the 16th Asian Test Symposium, 2007

2006

Diagnosis with Limited Failure Information.

[BibT_eX]

[DOI]

Proceedings of the 2006 IEEE International Test Conference, 2006

On N-Detect Pattern Set Optimization.

[BibT_eX]

[DOI]

Yu Huang

Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

Diagnosis of defects on scan enable and clock trees.

[BibT_eX]

[DOI]

Yu Huang

Keith Gallie

Proceedings of the Conference on Design, Automation and Test in Europe, 2006

2005

Compressed pattern diagnosis for scan chain failures.

[BibT_eX]

[DOI]

Yu Huang

Wu-Tung Cheng

Janusz Rajski

Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

Off-shore outsource DFT vs. build off-shore branch offices.

[BibT_eX]

[DOI]

Yu Huang

Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

Using fault model relaxation to diagnose real scan chain defects.

[BibT_eX]

[DOI]

Yu Huang

Wu-Tung Cheng

Greg Crowell

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004

Intermittent Scan Chain Fault Diagnosis Based on Signal Probability Analysis.

[BibT_eX]

[DOI]

Proceedings of the 2004 Design, 2004

Compactor Independent Direct Diagnosis.

[BibT_eX]

[DOI]

Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004

2003

SOC Test Scheduling Using Simulated Annealing.

[BibT_eX]

[DOI]

Proceedings of the 21st IEEE VLSI Test Symposium (VTS 2003), 27 April, 2003

Statistical Diagnosis for Intermittent Scan Chain Hold-Time Fault.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

Static Pin Mapping and SOC Test Scheduling for Cores with Multiple Test Sets.

[BibT_eX]

[DOI]

Proceedings of the 4th International Symposium on Quality of Electronic Design (ISQED 2003), 2003

Using embedded infrastructure IP for SOC post-silicon verification.

[BibT_eX]

[DOI]

Yu Huang

Wu-Tung Cheng

Proceedings of the 40th Design Automation Conference, 2003

Efficient Diagnosis for Multiple Intermittent Scan Chain Hold-Time Faults.

[BibT_eX]

[DOI]

Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003

2002

Synthesis of Scan Chains for Netlist Descriptions at RT-Level.

[BibT_eX]

[DOI]

J. Electron. Test., 2002

On Concurrent Test of Core-Based SOC Design.

[BibT_eX]

[DOI]

J. Electron. Test., 2002

Constraint Driven Pin Mapping for Concurrent SOC Testing.

[BibT_eX]

[DOI]

Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002

Optimal Core Wrapper Width Selection and SOC Test Scheduling Based on 3-D Bin Packing Algorithm.

[BibT_eX]

[DOI]

Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

Core - Clustering Based SOC Test Scheduling Optimization.

[BibT_eX]

[DOI]

Yu Huang

Sudhakar M. Reddy

Wu-Tung Cheng

Proceedings of the 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002

2001

On RTL scan design.

[BibT_eX]

[DOI]

Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

Effect of RTL coding style on testability.

[BibT_eX]

[DOI]

Proceedings of the IEEE 2001 Custom Integrated Circuits Conference, 2001

Resource Allocation and Test Scheduling for Concurrent Test of Core-Based SoC D.

[BibT_eX]

[DOI]

Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001

2000

Improving the Proportion of At-Speed Tests in Scan BIST.

[BibT_eX]

[DOI]

Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000

Yu Huang

Timeline

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