Improving the Proportion of At-Speed Tests in Scan BIST. - Yu Huang 005; Irith Pomeranz; Sudhakar M. Reddy; Janusz Rajski (ICCAD, 2000)

Resource Allocation and Test Scheduling for Concurrent Test of Core-Based SoC D. - Yu Huang 005; Wu-Tung Cheng; Chien-Chung Tsai; Nilanjan Mukherjee 001; Omer Samman; Yahya Zaidan; Sudhakar M. Reddy (Asian Test Symposium, 2001)

Effect of RTL coding style on testability. - Yu Huang 005; Chien-Chung Tsai; Nilanjan Mukherhee; Wu-Tung Cheng; Sudhakar M. Reddy (CICC, 2001)

On RTL scan design. - Yu Huang 005; Chien-Chung Tsai; Nilanjan Mukherjee 001; Omer Samman; Dan Devries; Wu-Tung Cheng; Sudhakar M. Reddy (ITC, 2001)

Core - Clustering Based SOC Test Scheduling Optimization. - Yu Huang 005; Sudhakar M. Reddy; Wu-Tung Cheng (Asian Test Symposium, 2002)

Optimal Core Wrapper Width Selection and SOC Test Scheduling Based on 3-D Bin Packing Algorithm. - Yu Huang 005; Sudhakar M. Reddy; Wu-Tung Cheng; Paul Reuter; Nilanjan Mukherjee 001; Chien-Chung Tsai; Omer Samman; Yahya Zaidan (ITC, 2002)

Constraint Driven Pin Mapping for Concurrent SOC Testing. - Yu Huang 005; Nilanjan Mukherjee 001; Chien-Chung Tsai; Omer Samman; Yahya Zaidan; Yanping Zhang; Wu-Tung Cheng; Sudhakar M. Reddy (ASP-DAC/VLSI Design, 2002)

On Concurrent Test of Core-Based SOC Design. - Yu Huang 005; Wu-Tung Cheng; Chien-Chung Tsai; Nilanjan Mukherjee 001; Omer Samman; Yahya Zaidan; Sudhakar M. Reddy (J. Electron. Test., 2002)

Synthesis of Scan Chains for Netlist Descriptions at RT-Level. - Yu Huang 005; Chien-Chung Tsai; Nilanjan Mukherjee 001; Omer Samman; Wu-Tung Cheng; Sudhakar M. Reddy (J. Electron. Test., 2002)

Efficient Diagnosis for Multiple Intermittent Scan Chain Hold-Time Faults. - Yu Huang 005; Wu-Tung Cheng; Cheng-Ju Hsieh; Huan-Yung Tseng; Alou Huang; Yu-Ting Hung (Asian Test Symposium, 2003)

Using embedded infrastructure IP for SOC post-silicon verification. - Yu Huang 005; Wu-Tung Cheng (DAC, 2003)

Static Pin Mapping and SOC Test Scheduling for Cores with Multiple Test Sets. - Yu Huang 005; Wu-Tung Cheng; Chien-Chung Tsai; Nilanjan Mukherjee 001; Sudhakar M. Reddy (ISQED, 2003)

Statistical Diagnosis for Intermittent Scan Chain Hold-Time Fault. - Yu Huang 005; Wu-Tung Cheng; Sudhakar M. Reddy; Cheng-Ju Hsieh; Yu-Ting Hung (ITC, 2003)

SOC Test Scheduling Using Simulated Annealing. - Wei Zou; Sudhakar M. Reddy; Irith Pomeranz; Yu Huang 005 (VTS, 2003)

Compactor Independent Direct Diagnosis. - Wu-Tung Cheng; Kun-Han Tsai; Yu Huang 005; Nagesh Tamarapalli; Janusz Rajski (Asian Test Symposium, 2004)

Intermittent Scan Chain Fault Diagnosis Based on Signal Probability Analysis. - Yu Huang 005; Wu-Tung Cheng; Cheng-Ju Hsieh; Huan-Yung Tseng; Alou Huang; Yu-Ting Hung (DATE, 2004)

Using fault model relaxation to diagnose real scan chain defects. - Yu Huang 005; Wu-Tung Cheng; Greg Crowell (ASP-DAC, 2005)

Off-shore outsource DFT vs. build off-shore branch offices. - Yu Huang 005 (ITC, 2005)

Compressed pattern diagnosis for scan chain failures. - Yu Huang 005; Wu-Tung Cheng; Janusz Rajski (ITC, 2005)

Diagnosis of defects on scan enable and clock trees. - Yu Huang 005; Keith Gallie (DATE, 2006)

On N-Detect Pattern Set Optimization. - Yu Huang 005 (ISQED, 2006)

Diagnosis with Limited Failure Information. - Yu Huang 005; Wu-Tung Cheng; Nagesh Tamarapalli; Janusz Rajski; Randy Klingenberg; Will Hsu; Yuan-Shih Chen (ITC, 2006)

Fault Dictionary Based Scan Chain Failure Diagnosis. - Ruifeng Guo; Yu Huang 005; Wu-Tung Cheng (ATS, 2007)

Programmable Logic BIST for At-speed Test. - Yu Huang 005; Xijiang Lin (ATS, 2007)

A RTL Testability Analyzer Based on Logical Virtual Prototyping. - Yu Huang 005; Nilanjan Mukherjee 001; Wu-Tung Cheng; Greg Aldrich (ATS, 2007)

Effect of IR-Drop on Path Delay Testing Using Statistical Analysis. - Chunsheng Liu; Yang Wu; Yu Huang 005 (ATS, 2007)

Scan Diagnosis and Its Successful Industrial Applications. - Wu Yang; Wu-Tung Cheng; Yu Huang 005; Martin Keim; Randy Klingenberg (ATS, 2007)

Dynamic learning based scan chain diagnosis. - Yu Huang 005 (DATE, 2007)

A complete test set to diagnose scan chain failures. - Ruifeng Guo; Yu Huang 005; Wu-Tung Cheng (ITC, 2007)

Diagnose compound scan chain and system logic defects. - Yu Huang 005; Wu-Tung Cheng; Ruifeng Guo; Will Hsu; Yuan-Shih Chen; Albert Mann (ITC, 2007)

Effects of Embedded Decompression and Compaction Architectures on Side-Channel Attack Resistance. - Chunsheng Liu; Yu Huang 005 (VTS, 2007)

Observation Point Oriented Deterministic Diagnosis Pattern Generation (DDPG) for Chain Diagnosis. - Fei Wang; Yu Hu 001; Yu Huang 005; Jing Ye 001; Xiaowei Li 001 (ATS, 2008)

Diagnose Multiple Stuck-at Scan Chain Faults. - Yu Huang 005; Wu-Tung Cheng; Ruifeng Guo (ETS, 2008)

Detection and Diagnosis of Static Scan Cell Internal Defect. - Ruifeng Guo; Liyang Lai; Yu Huang 005; Wu-Tung Cheng (ITC, 2008)

Deterministic Diagnostic Pattern Generation (DDPG) for Compound Defects. - Fei Wang; Yu Hu 001; Huawei Li 001; Xiaowei Li 001; Jing Ye 001; Yu Huang 005 (ITC, 2008)

Reducing Scan Shift Power at RTL. - Elif Alpaslan; Yu Huang 005; Xijiang Lin; Wu-Tung Cheng; Jennifer Dworak (VTS, 2008)

Survey of Scan Chain Diagnosis. - Yu Huang 005; Ruifeng Guo; Wu-Tung Cheng; James Chien-Mo Li (IEEE Des. Test Comput., 2008)

Scan Shift Power Reduction by Freezing Power Sensitive Scan Cells. - Xijiang Lin; Yu Huang 005 (J. Electron. Test., 2008)

Scan Chain Diagnosis by Adaptive Signal Profiling with Manufacturing ATPG Patterns. - Yu Huang 005; Wu-Tung Cheng; Ruifeng Guo; Ting-Pu Tai; Feng-Ming Kuo; Yuan-Shih Chen (Asian Test Symposium, 2009)

On Improving Diagnostic Test Generation for Scan Chain Failures. - Xun Tang; Ruifeng Guo; Wu-Tung Cheng; Sudhakar M. Reddy; Yu Huang 005 (Asian Test Symposium, 2009)

Emulating and diagnosing IR-drop by using dynamic SDF. - Ke Peng; Yu Huang 005; Ruifeng Guo; Wu-Tung Cheng; Mohammad Tehranipoor (ASP-DAC, 2010)

Enhance Profiling-Based Scan Chain Diagnosis by Pattern Masking. - Wu-Tung Cheng; Yu Huang 005 (Asian Test Symposium, 2010)

Full-circuit SPICE simulation based validation of dynamic delay estimation. - Ke Peng; Yu Huang 005; Pinki Mallick; Wu-Tung Cheng; Mohammad Tehranipoor (ETS, 2010)

Case study of scan chain diagnosis and PFA on a low yield wafer. - Yu Huang 005; Brady Benware; Wu-Tung Cheng; Ting-Pu Tai; Feng-Ming Kuo; Yuan-Shih Chen (ITC, 2010)

Test cycle power optimization for scan-based designs. - Kun-Han Tsai; Yu Huang 005; Wu-Tung Cheng; Ting-Pu Tai; Augusli Kifli (ITC, 2010)

On Reducing Scan Shift Activity at RTL. - Elif Alpaslan; Yu Huang 005; Xijiang Lin; Wu-Tung Cheng; Jennifer Dworak (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010)

A Hybrid Flow for Memory Failure Bitmap Classification. - Jianbo Li; Yu Huang 005; Wu-Tung Cheng; Chris Schuermyer; Dong Xiang; Eric Faehn; Ruth Farrugia (Asian Test Symposium, 2012)

Improved volume diagnosis throughput using dynamic design partitioning. - Xiaoxin Fan; Huaxing Tang; Yu Huang 005; Wu-Tung Cheng; Sudhakar M. Reddy; Brady Benware (ITC, 2012)

EDT bandwidth management - Practical scenarios for large SoC designs. - Jakub Janicki; Jerzy Tyszer; Wu-Tung Cheng; Yu Huang 005; Mark Kassab; Nilanjan Mukherjee 001; Janusz Rajski; Yan Dong; Grady Giles (ITC, 2013)

Distributed dynamic partitioning based diagnosis of scan chain. - Yu Huang 005; Xiaoxin Fan; Huaxing Tang; Manish Sharma; Wu-Tung Cheng; Brady Benware; Sudhakar M. Reddy (VTS, 2013)

Bit selection algorithm suitable for high-volume production of SRAM-PUF. - Kan Xiao; Md. Tauhidur Rahman 001; Domenic Forte; Yu Huang 005; Mei Su 002; Mohammad Tehranipoor (HOST, 2014)

Test Compression Improvement with EDT Channel Sharing in SoC Designs. - Yu Huang 005; Mark Kassab; Jay Jahangiri; Janusz Rajski; Wu-Tung Cheng; Dongkwan Han; Jihye Kim 002; Kun Young Chung (NATW, 2014)

Diagnose Failures Caused by Multiple Locations at a Time. - Jing Ye 001; Yu Hu 001; Xiaowei Li 001; Wu-Tung Cheng; Yu Huang 005; Huaxing Tang (IEEE Trans. Very Large Scale Integr. Syst., 2014)

Advancements in diagnosis driven yield analysis (DDYA): A survey of state-of-the-art scan diagnosis and yield analysis technologies. - Yu Huang 005; Wu Yang; Wu-Tung Cheng (ETS, 2015)

Hybrid Hierarchical and Modular Tests for SoC Designs. - Guoliang Li 004; Jun Qian; Qinfu Yang; Yuan Zuo; Rui Li 084; Yu Huang 005; Mark Kassab; Janusz Rajski (NATW, 2015)

Scan Test Bandwidth Management for Ultralarge-Scale System-on-Chip Architectures. - Wu-Tung Cheng; Yan Dong; Grady Giles; Yu Huang 005; Jakub Janicki; Mark Kassab; Grzegorz Mrugalski; Nilanjan Mukherjee 001; Janusz Rajski; Jerzy Tyszer (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Diagnosis and Layout Aware (DLA) Scan Chain Stitching. - Jing Ye 001; Yu Huang 005; Yu Hu 001; Wu-Tung Cheng; Ruifeng Guo; Liyang Lai; Ting-Pu Tai; Xiaowei Li 001; Wei-pin Changchien; Daw-Ming Lee; Ji-Jan Chen; Sandeep C. Eruvathi; et al. (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Scan Chain Diagnosis Based on Unsupervised Machine Learning. - Yu Huang 005; Brady Benware; Randy Klingenberg; Huaxing Tang; Jayant Dsouza; Wu-Tung Cheng (ATS, 2017)

On designing two-dimensional scan architecture for test chips. - Yu Huang 005; Wu-Tung Cheng (VLSI-DAT, 2017)

Industrial Case Studies of SoC Test Scheduling Optimization by Selecting Appropriate EDT Architectures. - Guoliang Li 004; Henry Zhao; Qinfu Yang; Jun Qian; Yu Huang 005 (ITC-Asia, 2018)

Hypercompression of Test Patterns. - Yu Huang 005; Sylwester Milewski; Janusz Rajski; Jerzy Tyszer; Chen Wang 014 (ITC, 2018)

Special session on machine learning for test and diagnosis. - Krishnendu Chakrabarty; Li-C. Wang; Gaurav Veda; Yu Huang 005 (VTS, 2018)

Innovative practices on machine learning for emerging applications. - Kareem Madkour; Zhaobo Zhang; Alfred L. Crouch; Peter L. Levin; Eve Hunter; Yu Huang 005 (VTS, 2018)

Improving scan chain diagnostic accuracy using multi-stage artificial neural networks. - Mason Chern; Shih-Wei Lee; Shi-Yu Huang; Yu Huang 005; Gaurav Veda; Kun-Han Hans Tsai; Wu-Tung Cheng (ASP-DAC, 2019)

Deep Learning Based Test Compression Analyzer. - Cheng-Hung Wu; Yu Huang 005; Kuen-Jong Lee; Wu-Tung Cheng; Gaurav Veda; Sudhakar M. Reddy; Chun-Cheng Hu; Chong-Siao Ye (ATS, 2019)

Non-Adaptive Pattern Reordering to Improve Scan Chain Diagnostic Resolution. - Yu Huang 005; Jakub Janicki; Szczepan Urban (ETS, 2019)

A Case Study of Testing Strategy for AI SoC. - Haiying Ma; Rui Guo; Quan Jing; Jing Han; Yu Huang 005; Rahul Singhal; Wu Yang; Xin Wen; Fanjin Meng (ITC-Asia, 2019)

Tutorial 1B: AI Chip Technologies and DFT Methodologies. - Yu Huang 005; Rahul Singhal (SoCC, 2019)

Reversible Scan Based Diagnostic Patterns. - Yu Huang 005; Szczepan Urban; Wu-Tung Cheng; Manish Sharma; Fengju Niu; Junna Zhong; Wen-Lung Hsu (VLSI-DAT, 2019)

Innovative Practices on DFT for AI Chips. - Iris Ma; Hui King Lau; Joseph A. Reynick; Yu Huang 005 (VTS, 2019)

Efficient Prognostication of Pattern Count with Different Input Compression Ratios. - Fong-Jyun Tsai; Chong-Siao Ye; Yu Huang 005; Kuen-Jong Lee; Wu-Tung Cheng; Sudhakar M. Reddy; Mark Kassab; Janusz Rajski (ETS, 2020)

Estimation of Test Data Volume for Scan Architectures with Different Numbers of Input Channels. - Fong-Jyun Tsai; Chong-Siao Ye; Yu Huang 005; Kuen-Jong Lee; Wu-Tung Cheng; Sudhakar M. Reddy; Mark Kassab; Janusz Rajski; Shi-Xuan Zheng (ITC-Asia, 2020)

Fast Bring-Up of an AI SoC through IEEE 1687 Integrating Embedded TAPs and IEEE 1500 Interfaces. - Haiying Ma; Ligang Lu; Haitao Qian; Jing Han; Xin Wen; Fanjin Meng; Rahul Singhal; Martin Keim; Yu Huang 005; Wu Yang (ITC, 2020)

Prediction of Test Pattern Count and Test Data Volume for Scan Architectures under Different Input Channel Configurations. - Fong-Jyun Tsai; Chong-Siao Ye; Kuen-Jong Lee; Shi-Xuan Zheng; Yu Huang 005; Wu-Tung Cheng; Sudhakar M. Reddy; Mark Kassab; Janusz Rajski; Chen Wang 014; Justyna Zawada (ITC, 2020)

Effective Design of Layout-Friendly EDT Decompressor. - Yu Huang 005; Janusz Rajski; Mark Kassab; Nilanjan Mukherjee 001; Jeffrey Mayer (VTS, 2020)

Diagnosis of Intermittent Scan Chain Faults Through a Multistage Neural Network Reasoning Process. - Mason Chern; Shih-Wei Lee; Shi-Yu Huang; Yu Huang 005; Gaurav Veda; Kun-Han Tsai; Wu-Tung Cheng (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Low Cost Hypercompression of Test Data. - Yu Huang 005; Sylwester Milewski; Janusz Rajski; Jerzy Tyszer; Chen Wang 014 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Diagnosis and Yield Learning. - Yu Huang 005; Wu-Tung Cheng; Ruifeng Guo; Sameer Chillarige (ITC-Asia, 2021)

Automotive Test and Reliability. - Yu Huang 005; David Francis; Yervant Zorian; Nilanjan Mukherjee 001 (ITC-Asia, 2021)

Testability-Aware Low Power Controller Design with Evolutionary Learning. - Min Li 019; Zhengyuan Shi; Zezhong Wang 006; Weiwei Zhang; Yu Huang 005; Qiang Xu 001 (ITC, 2021)

Special Session - Test for AI Chips: from DFT to On-line Testing. - Huawei Li 001; Xiaowei Li 001; Yu Huang 005; Ying Wang 001; Gary Guo (VTS, 2021)

Representation Learning of Logic Circuits. - Min Li 019; Sadaf Khan; Zhengyuan Shi; Naixing Wang; Yu Huang 005; Qiang Xu 001 (CoRR, 2021)

Accelerate SAT-based ATPG via Preprocessing and New Conflict Management Heuristics. - Junhua Huang; Hui-Ling Zhen; Naixing Wang; Mingxuan Yuan; Hui Mao; Yu Huang 005; Jiping Tao (ASP-DAC, 2022)

Functionality matters in netlist representation learning. - Ziyi Wang 010; Chen Bai; Zhuolun He; Guangliang Zhang; Qiang Xu 001; Tsung-Yi Ho; Bei Yu 001; Yu Huang 005 (DAC, 2022)

LHNN: lattice hypergraph neural network for VLSI congestion prediction. - Bowen Wang; Guibao Shen; Dong Li 016; Jianye Hao; Wulong Liu; Yu Huang 005; Hongzhong Wu; Yibo Lin; Guangyong Chen; Pheng-Ann Heng (DAC, 2022)

RCANet: Root Cause Analysis via Latent Variable Interaction Modeling for Yield Improvement. - Xiaopeng Zhang 009; Shoubo Hu; Zhitang Chen; Shengyu Zhu 001; Evangeline F. Y. Young; Pengyun Li; Cheng Chen; Yu Huang 005; Jianye Hao (ITC, 2022)

Neural Fault Analysis for SAT-based ATPG. - Junhua Huang; Hui-Ling Zhen; Naixing Wang; Hui Mao; Mingxuan Yuan; Yu Huang 005 (ITC, 2022)

DeepTPI: Test Point Insertion with Deep Reinforcement Learning. - Zhengyuan Shi; Min Li 019; Sadaf Khan; Liuzheng Wang; Naixing Wang; Yu Huang 005; Qiang Xu 001 (ITC, 2022)

Compression-Aware ATPG. - Xing Wang; Zezhong Wang 006; Naixing Wang; Weiwei Zhang; Yu Huang 005 (ITC, 2022)

TOFU: A Two-Step Floorplan Refinement Framework for Whitespace Reduction. - Shixiong Kai; Chak-Wa Pui; Fangzhou Wang; Shougao Jiang; Bin Wang 034; Yu Huang 005; Jianye Hao (DATE, 2023)

EffiSyn: Efficient Logic Synthesis with Dynamic Scoring and Pruning. - Xing Li; Lei Chen 002; Jiantang Zhang; Shuang Wen 007; Weihua Sheng; Yu Huang 005; Mingxuan Yuan (ICCAD, 2023)

Conflict-driven Structural Learning Towards Higher Coverage Rate in ATPG. - Hui-Ling Zhen; Naixing Wang; Junhua Huang; Xinyue Huang; Mingxuan Yuan; Yu Huang 005 (CoRR, 2023)

A Unified Framework for Layout Pattern Analysis With Deep Causal Estimation. - Ran Chen 001; Shoubo Hu; Zhitang Chen; Shengyu Zhu 001; Bei Yu 001; Pengyun Li; Cheng Chen; Yu Huang 005; Jianye Hao (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

BetterV: Controlled Verilog Generation with Discriminative Guidance. - Zehua Pei; Hui-Ling Zhen; Mingxuan Yuan; Yu Huang 005; Bei Yu 001 (ICML, 2024)

Large circuit models: opportunities and challenges. - Lei Chen; Yiqi Chen; Zhufei Chu; Wenji Fang; Tsung-Yi Ho; Ru Huang 001; Yu Huang 005; Sadaf Khan; Min Li; Xingquan Li; Yu Li; Yun Liang 001; et al. (Sci. China Inf. Sci., 2024)

Erratum to: Large circuit models: opportunities and challenges. - Lei Chen; Yiqi Chen; Zhufei Chu; Wenji Fang; Tsung-Yi Ho; Ru Huang 001; Yu Huang 005; Sadaf Khan; Min Li; Xingquan Li; Yu Li; Yun Liang 001; et al. (Sci. China Inf. Sci., 2024)

The Dawn of AI-Native EDA: Promises and Challenges of Large Circuit Models. - Lei Chen 002; Yiqi Chen; Zhufei Chu; Wenji Fang; Tsung-Yi Ho; Yu Huang 005; Sadaf Khan; Min Li 019; Xingquan Li; Yun Liang 001; Yibo Lin; Jinwei Liu; et al. (CoRR, 2024)

HDLdebugger: Streamlining HDL debugging with Large Language Models. - Xufeng Yao; Haoyang Li 002; Tsz Ho Chan; Wenyi Xiao; Mingxuan Yuan; Yu Huang 005; Lei Chen 002; Bei Yu 001 (CoRR, 2024)

FGNN2: A Powerful Pretraining Framework for Learning the Logic Functionality of Circuits. - Ziyi Wang 010; Chen Bai; Zhuolun He; Guangliang Zhang; Qiang Xu 001; Tsung-Yi Ho; Yu Huang 005; Bei Yu 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)