Yu Ji

According to our database1, Yu Ji authored at least 12 papers between 2016 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.



In proceedings 
PhD thesis 


On csauthors.net:


NNBench-X: Benchmarking and Understanding Neural Network Workloads for Accelerator Designs.
Computer Architecture Letters, 2019

Memory Trojan Attack on Neural Network Accelerators.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

FPSA: A Full System Stack Solution for Reconfigurable ReRAM-based NN Accelerator Architecture.
Proceedings of the Twenty-Fourth International Conference on Architectural Support for Programming Languages and Operating Systems, 2019

Crossbar-Aware Neural Network Pruning.
IEEE Access, 2018

TETRIS: TilE-matching the TRemendous Irregular Sparsity.
Proceedings of the Advances in Neural Information Processing Systems 31: Annual Conference on Neural Information Processing Systems 2018, 2018

SNrram: an efficient sparse neural network computation architecture based on resistive random-access memory.
Proceedings of the 55th Annual Design Automation Conference, 2018

Bridge the Gap between Neural Networks and Neuromorphic Hardware with a Neural Network Compiler.
Proceedings of the Twenty-Third International Conference on Architectural Support for Programming Languages and Operating Systems, 2018

POSTER: Bridge the Gap Between Neural Networks and Neuromorphic Hardware.
Proceedings of the 26th International Conference on Parallel Architectures and Compilation Techniques, 2017

Modelling Spiking Neural Network from the Architecture Evaluation Perspective.
J. Comput. Sci. Technol., 2016

NEUTRAMS: Neural network transformation and co-design under neuromorphic hardware constraints.
Proceedings of the 49th Annual IEEE/ACM International Symposium on Microarchitecture, 2016

Optimized Mapping Spiking Neural Networks onto Network-on-Chip.
Proceedings of the Algorithms and Architectures for Parallel Processing, 2016

Neural network transformation under hardware constraints.
Proceedings of the 2016 International Conference on Compilers, 2016