Design of STR level converters for SoCs using the multi-island dual-VDD design technique. - Jinn-Shyan Wang; Yu-Juey Chang; Chingwei Yeh; Yuan-Hua Chu (ISCAS, 2006)

Heuristic Sizing Methodology for Designing High-Performance CMOS Level Converters with Balanced Rise and Fall Delays. - Jinn-Shyan Wang; Yu-Juey Chang; Chingwei Yeh (IEICE Trans. Electron., 2010)

Design of High-Performance CMOS Level Converters Considering PVT Variations. - Jinn-Shyan Wang; Yu-Juey Chang; Chingwei Yeh (IEICE Trans. Electron., 2011)