A 1V 11b 200MS/s Pipelined ADC with Digital Background Calibration in 65nm CMOS. - Kang-Wei Hsueh; Yu-Kai Chou; Yu-Hsuan Tu; Yi-Fu Chen; Ya-Lun Yang; Hung-Sung Li (ISSCC, 2008)

A power management unit integrated ADSL/ADSL2+ CPE analog front-end with -93.5dB THD for DMT-based applications. - Yu-Kai Chou; Yue Feng; Yu-Hsin Lin; Cong Liu 016; Chen-Yen Ho; Bo Hu; Jun Zha; Steven Chuang (A-SSCC, 2014)

A Time-Interleaved Statistically-Driven Two-Step Flash ADC for High-Speed Wireline Applications. - Dengbao Liu; Lin He 003; Fujiang Lin; Ting Li; Yu-Kai Chou (J. Circuits Syst. Comput., 2017)