Reconfigurable Hardware Architecture Design and Implementation for AI Deep Learning Accelerator. - Chung-Bin Wu; Ching-Shun Wang; Yu-Kuan Hsiao (GCCE, 2020)

Cordic Based Hardware Implementation for Object Region Layer of Yolo V2. - Chung-Bin Wu; Yu-Kuan Hsiao (ICCE-TW, 2020)

High Efficient Bandwidth Utilization Hardware Design and Implement for AI Deep Learning Accelerator. - Chung-Bin Wu; Yin-Tsung Hwang; Yu-Cheng Hsueh; Yu-Kuan Hsiao (ISOCC, 2020)

Extensible and Modularized Processing Unit Design and Implementation for AI Accelerator. - Chung-Bin Wu; Yu-Kuan Hsiao; Wei-Hsuan Chang (AICAS, 2022)