Designs of the basic block reassembling Instruction Stream Buffer for X86 ISA. - Jih-Ching Chiu; Yu-Liang Chou; Ta-Li Yeh; Tseng-Kuei Lin (ACSAC, 2008)

The Multi-context Reconfigurable Processing Unit for Fine-grain Computing. - Jih-Ching Chiu; Yu-Liang Chou; Ren-Bang Lin (J. Inf. Sci. Eng., 2008)

A multi-streaming SIMD architecture for multimedia applications. - Jih-Ching Chiu; Yu-Liang Chou; Hua-Yi Tzeng (Conf. Computing Frontiers, 2009)

Design of a novel SIMD architecture by fusing operations and registers. - Jih-Ching Chiu; Kai-Ming Yang; Yu-Liang Chou (ICS, 2009)

A hyperscalar multi-core architecture. - Jih-Ching Chiu; Yu-Liang Chou; Ding-Siang Su (Conf. Computing Frontiers, 2010)

Hyperscalar: A Novel Dynamically Reconfigurable Multi-core Architecture. - Jih-Ching Chiu; Yu-Liang Chou; Po-Kai Chen (ICPP, 2010)

The Basic Block Reassembling Instruction Stream Buffer with LWBTB for X86 ISA. - Jih-Ching Chiu; Yu-Liang Chou; Tseng-Kuei Lin (J. Inf. Sci. Eng., 2010)

A multi-streaming SIMD multimedia computing engine. - Jih-Ching Chiu; Yu-Liang Chou (Microprocess. Microsystems, 2010)

A Unitable Computing Architecture for Chip Multiprocessors. - Jih-Ching Chiu; Yu-Liang Chou; Po-Kai Chen; Ding-Siang Su (Comput. J., 2011)

OCP: Offload Co-Processor for energy efficiency in embedded mobile systems. - Jie Tang 003; Chen Liu 001; Yu-Liang Chou; Shaoshan Liu (ASAP, 2013)

A relation-exchanging buffering mechanism for instruction and data streaming. - Jih-Ching Chiu; Kai-Ming Yang; Yu-Liang Chou; Chih-Kang Wu (Comput. Electr. Eng., 2013)

A hyperscalar dual-core architecture for embedded systems. - Jih-Ching Chiu; Kai-Ming Yang; Yu-Liang Chou (Microprocess. Microsystems, 2013)

An Energy and Performance Efficient DVFS Scheme for Irregular Parallel Divide-and-Conquer Algorithms on the Intel SCC. - Yu-Liang Chou; Shaoshan Liu; Eui-Young Chung; Jean-Luc Gaudiot (IEEE Comput. Archit. Lett., 2014)

An Interpretable Probabilistic Approach for Demystifying Black-box Predictive Models. - Catarina Moreira; Yu-Liang Chou; Mythreyi Velmurugan; Chun Ouyang 001; Renuka Sindhgatta; Peter Bruza (CoRR, 2020)

LINDA-BN: An interpretable probabilistic approach for demystifying black-box predictive models. - Catarina Moreira; Yu-Liang Chou; Mythreyi Velmurugan; Chun Ouyang 001; Renuka Sindhgatta; Peter Bruza (Decis. Support Syst., 2021)

Benchmark Evaluation of Counterfactual Algorithms for XAI: From a White Box to a Black Box. - Yu-Liang Chou; Chihcheng Hsieh; Catarina Moreira; Chun Ouyang 001; Joaquim Jorge 001; João Madeiras Pereira (CoRR, 2022)

Counterfactuals and causability in explainable artificial intelligence: Theory, algorithms, and applications. - Yu-Liang Chou; Catarina Moreira; Peter Bruza; Chun Ouyang 001; Joaquim Jorge 001 (Inf. Fusion, 2022)

Benchmarking Instance-Centric Counterfactual Algorithms for XAI: From White Box to Black Box. - Catarina Moreira; Yu-Liang Chou; Chihcheng Hsieh; Chun Ouyang 001; João Pereira 001; Joaquim Jorge 001 (ACM Comput. Surv., 2025)