Graph based analysis of FPGA routing. - Yu-Liang Wu; Malgorzata Marek-Sadowska (EURO-DAC, 1993)

An Efficient Router for 2-D Field Programmable Gate Arrays. - Yu-Liang Wu; Malgorzata Marek-Sadowska (EDAC-ETC-EUROASIC, 1994)

On computational complexity of a detailed routing problem in two dimensional FPGAs. - Yu-Liang Wu; Shuji Tsukiyama; Malgorzata Marek-Sadowska (Great Lakes Symposium on VLSI, 1994)

On the NP-completeness of regular 2-D FPGA routing architectures and a novel solution. - Yu-Liang Wu; Douglas Chang (ICCAD, 1994)

Routing on regular segmented 2-D FPGAs. - Yu-Liang Wu; Malgorzata Marek-Sadowska (ASP-DAC, 1995)

Orthogonal Greedy Coupling - A New Optimization Approach to 2-D FPGA Routing. - Yu-Liang Wu; Malgorzata Marek-Sadowska (DAC, 1995)

Graph based analysis of 2-D FPGA routing. - Yu-Liang Wu; Shuji Tsukiyama; Malgorzata Marek-Sadowska (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996)

Not necessarily more switches more routability [sic.]. - Yu-Liang Wu; Douglas Chang; Malgorzata Marek-Sadowska; Shuji Tsukiyama (ASP-DAC, 1997)

Routing for array-type FPGA's. - Yu-Liang Wu; Malgorzata Marek-Sadowska (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997)

On the Optimal Sub-routing Structures of 2-D FPGA Greedy Routing Architectures. - Jiaofeng Pan; Yu-Liang Wu; C. K. Wong (ASP-DAC, 1998)

On thin Boolean functions and related optimum OBDD ordering. - Yu-Liang Wu; Hongbing Fan; C. K. Wong (ICCD, 1998)

A tree-structured LFSR synthesis scheme for pseudo-exhaustive testing of VLSI circuits. - Wen-Ben Jone; Jiann-Chyi Rau; Shih-Chieh Chang; Yu-Liang Wu (ITC, 1998)

On the optimal four-way switch box routing structures of FPGA greedy routing architectures1. - Jiaofeng Pan; Yu-Liang Wu; C. K. Wong; Guiying Yan (Integr., 1998)

A Cogitative Algorithm for Solving the Equal Circles Packing Problem. - Wenqi Huang 001; Yu-Liang Wu; C. K. Wong (Handbook of Combinatorial Optimization, 1999)

On the Testing Quality of Random and Pseudo-random Sequences for Permanent and Intermittent Faults. - Jin Ding; Yu-Liang Wu (ASP-DAC, 1999)

IBAW: an implication-tree based alternative-wiring logic transformation algorithm. - Wangning Long; Yu-Liang Wu; Jinian Bian (ASP-DAC, 2000)

Circuit partitioning with coupled logic restructuring techniques. - Yu-Liang Wu; Xiao-Long Yuan; David Ihsin Cheng (ASP-DAC, 2000)

General Models for Optimum Arbitrary-Dimension FPGA Switch Box Designs. - Hongbing Fan; Jiping Liu; Yu-Liang Wu (ICCAD, 2000)

A global routing model for universal switch box design. - Hongbing Fan; Jiping Liu; Yu-Liang Wu (ICECS, 2000)

On improved graph-based alternative wiring scheme for multi-level logic optimization. - Yu-Liang Wu; Chin Ngai Sze; Chak-Chung Cheung; Hongbing Fan (ICECS, 2000)

A Fast Graph-Based Alternative Wiring Scheme for Boolean Networks. - Yu-Liang Wu; Wangning Long; Hongbing Fan (VLSI Design, 2000)

OBDD Minimization Based on Two-Level Representation of Boolean Functions. - Yu-Liang Wu; Hongbing Fan; Malgorzata Marek-Sadowska; C. K. Wong (IEEE Trans. Computers, 2000)

Combinatorial routing analysis and design of universal switch blocks. - Hongbing Fan; Jiping Liu; Yu-Liang Wu (ASP-DAC, 2001)

Improved alternative wiring scheme applying dominator relationship. - Chin Ngai Sze; Yu-Liang Wu (ASP-DAC, 2001)

On Optimum Switch Box Designs for 2-D FPGAs. - Hongbing Fan; Jiping Liu; Yu-Liang Wu; Chak-Chung Cheung (DAC, 2001)

Further improve circuit partitioning using GBAW logic perturbation techniques. - Chak-Chung Cheung; Yu-Liang Wu; David Ihsin Cheng (DATE, 2001)

On Fixed Edges and Edge-Reconstruction of Series-Parallel Networks. - Hongbing Fan; Yu-Liang Wu; C. K. Wong (Graphs Comb., 2001)

On Optimum Designs of Universal Switch Blocks. - Hongbing Fan; Jiping Liu; Yu-Liang Wu; Chak-Chung Cheung (FPL, 2002)

An effective quasi-human based heuristic for solving the rectangle packing problem. - Yu-Liang Wu; Wenqi Huang 001; Siu-Chung Lau; C. K. Wong; Gilbert H. Young (Eur. J. Oper. Res., 2002)

Accelerating Logic Rewiring Using Implication Analysis Tree. - Chin Ngai Sze; Wangning Long; Yu-Liang Wu; Jinian Bian (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002)

Comment on Generic Universal Switch Blocks. - Hongbing Fan; Yu-Liang Wu; Yao-Wen Chang (IEEE Trans. Computers, 2002)

Reduction design for generic universal switch blocks. - Hongbing Fan; Jiping Liu; Yu-Liang Wu; C. K. Wong (ACM Trans. Design Autom. Electr. Syst., 2002)

On improving FPGA routability applying multi-level switch boxes. - Jiping Liu; Hongbing Fan; Yu-Liang Wu (ASP-DAC, 2003)

A cost-effective scan architecture for scan testing with non-scan test power and test application cost. - Dong Xiang; Shan Gu; Jia-Guang Sun; Yu-Liang Wu (DAC, 2003)

An Efficient Exact Router for Hyper-Universal Switching Box. - Jiping Liu; Hongbing Fan; Dinah de Porto; Yu-Liang Wu (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003)

General Models and a Reduction Design Technique for FPGA Switch Box Designs. - Hongbing Fan; Jiping Liu; Yu-Liang Wu (IEEE Trans. Computers, 2003)

On optimal hyperuniversal and rearrangeable switch box designs. - Hongbing Fan; Jiping Liu; Yu-Liang Wu; Chak-Chung Cheung (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003)

Further improve circuit partitioning using GBAW logic perturbation techniques. - Yu-Liang Wu; Chak-Chung Cheung; David Ihsin Cheng; Hongbing Fan (IEEE Trans. Very Large Scale Integr. Syst., 2003)

Scan-Based BIST Using an Improved Scan Forest Architecture. - Dong Xiang; Ming-Jing Chen; Kaiwei Li; Yu-Liang Wu (Asian Test Symposium, 2004)

On Optimal Irregular Switch Box Designs. - Hongbing Fan; Yu-Liang Wu; Chak-Chung Cheung; Jiping Liu (FPL, 2004)

A Less Flexibility First Based Algorithm for the Container Loading Problem. - Yuen-Ting Wu; Yu-Liang Wu (OR, 2004)

Crossbar based design schemes for switch boxes and programmable interconnection networks. - Hongbing Fan; Yu-Liang Wu (ASP-DAC, 2005)

Design and Analysis of Self-Repairable MEMS Accelerometer. - Xingguo Xiong; Yu-Liang Wu; Wen-Ben Jone (DFT, 2005)

FPGA technology mapping optimization by rewiring algorithms. - Wai-Chung Tang; Wing-Hang Lo; Yu-Liang Wu; Shih-Chieh Chang (ISCAS (6), 2005)

On Improved Least Flexibility First Heuristics Superior for Packing and Stock Cutting Problems. - Yu-Liang Wu; Chi-Kong Chan (SAGA, 2005)

A dual-mode built-in self-test technique for capacitive MEMS devices. - Xingguo Xiong; Yu-Liang Wu; Wen-Ben Jone (IEEE Trans. Instrum. Meas., 2005)

Reliability Analysis of Self-Repairable MEMS Accelerometer. - Xingguo Xiong; Yu-Liang Wu; Wen-Ben Jone (DFT, 2006)

Decomposition Design Theory and Methodology for Arbitrary-Shaped Switch Boxes. - Hongbing Fan; Yu-Liang Wu; Ray Chak-Chung Cheung; Jiping Liu (IEEE Trans. Computers, 2006)

How Much Can Logic Perturbation Help from Netlist to Final Routing for FPGAs. - Catherine L. Zhou; Wai-Chung Tang; Wing-Hang Lo; Yu-Liang Wu (DAC, 2007)

Further Improve Excellent Graph-Based FPGA Technology Mapping by Rewiring. - Wai-Chung Tang; Wing-Hang Lo; Yu-Liang Wu (ISCAS, 2007)

The exact channel density and compound design for generic universal switch blocks. - Hongbing Fan; Jiping Liu; Yu-Liang Wu; Chak-Chung Cheung (ACM Trans. Design Autom. Electr. Syst., 2007)

Control Circuitry for Self-Repairable MEMS Accelerometers. - Xingguo Xiong; Yu-Liang Wu; Wen-Ben Jone (EIAT/IETA, 2008)

Algorithms and Implementation for Interconnection Graph Problem. - Hongbing Fan; Christian Hundt 001; Yu-Liang Wu; Jason Ernst (COCOA, 2008)

Material Fatigue and Reliability of MEMS Accelerometers. - Xingguo Xiong; Yu-Liang Wu; Wen-Ben Jone (DFT, 2008)

A Quantitative Study of the Routing Architecture Exploring Routing Locality Property for Better Performance and Routability. - Wai-Chung Tang; Catherine L. Zhou; Yu-Liang Wu (ERSA, 2008)

Interconnection Graph Problem. - Hongbing Fan; Yu-Liang Wu (FCS, 2008)

Customized Reconfigurable Interconnection Networks for multiple application SOCS. - Hongbing Fan; Jason Ernst; Yu-Liang Wu (FPL, 2008)

The Vertex Linear Arboricity of Claw-Free Graphs with Small Degree. - Jian-Liang Wu 001; Yu-Liang Wu (Ars Comb., 2008)

A New Approach for Rearrangeable Multicast Switching Networks. - Hongbing Fan; Yu-Liang Wu (COCOA, 2009)

Design Automation for Reconfigurable Interconnection Networks. - Hongbing Fan; Yu-Liang Wu; Chak-Chung Cheung (ARC, 2010)

Structured Overlay Network for File Distribution. - Hongbing Fan; Yu-Liang Wu (COCOA (2), 2010)

ECR: a low complexity generalized error cancellation rewiring scheme. - Xiaoqing Yang; Tak-Kei Lam; Yu-Liang Wu (DAC, 2010)

Logic synthesis for low power using clock gating and rewiring. - Tak-Kei Lam; Steve Yang; Wai-Chung Tang; Yu-Liang Wu (ACM Great Lakes Symposium on VLSI, 2010)

Improving redundancy addition and removal using unreachable states for sequential circuits. - Xiaoqing Yang; Zigang Xiao; Yu-Liang Wu (ISCAS, 2010)

On applying erroneous clock gating conditions to further cut down power. - Tak-Kei Lam; Xiaoqing Yang; Wai-Chung Tang; Yu-Liang Wu (ASP-DAC, 2011)

A Fast Retiming Algorithm Integrated with Rewiring for Flip-Flop Reductions. - Yi Diao; Yu-Liang Wu (CAD/Graphics, 2011)

On Structural Analysis and Efficiency for Graph-Based Rewiring Techniques. - Fu-Shing Chim; Tak-Kei Lam; Yu-Liang Wu; Hongbing Fan (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011)

R-NoC: An Efficient Packet-Switched Reconfigurable Networks-on-Chip. - Hongbing Fan; Yue-Ang Chen; Yu-Liang Wu (ARC, 2012)

ECO timing optimization with negotiation-based re-routing and logic re-structuring using spare cells. - Xing Wei; Wai-Chung Tang; Yi Diao; Yu-Liang Wu (ASP-DAC, 2012)

Almost every wire is removable: A modeling and solution for removing any circuit wire. - Xiaoqing Yang; Tak-Kei Lam; Wai-Chung Tang; Yu-Liang Wu (DATE, 2012)

WRIP: logic restructuring techniques for wirelength-driven incremental placement. - Xing Wei; Wai-Chung Tang; Yu-Liang Wu; Cliff C. N. Sze; Charles J. Alpert (ACM Great Lakes Symposium on VLSI, 2012)

ECR: A Powerful and Low-Complexity Error Cancellation Rewiring Scheme. - Tak-Kei Lam; Wai-Chung Tang; Xiaoqing Yang; Yu-Liang Wu (ACM Trans. Design Autom. Electr. Syst., 2012)

Mountain-mover: An intuitive logic shifting heuristic for improving timing slack violating paths. - Xing Wei; Wai-Chung Tang; Yu-Liang Wu; Cliff C. N. Sze; Charles J. Alpert (ASP-DAC, 2013)

A cross-layer fault-tolerant design method for high manufacturing yield and system reliability. - Jianghao Guo; Qiang Han; Wen-Ben Jone; Yu-Liang Wu (DFTS, 2013)

Design Automation Framework for Reconfigurable Interconnection Networks. - Hongbing Fan; Yu-Liang Wu; Ray C. C. Cheung (Comput. J., 2013)

Testing of Synchronizers in Asynchronous FIFO. - Hyoung-Kook Kim; Laung-Terng Wang; Yu-Liang Wu; Wen-Ben Jone (J. Electron. Test., 2013)

On macro-fault: a new fault model, its implications on fault tolerance and manufacturing yield. - Tak-Kei Lam; Xing Wei; Wen-Ben Jone; Yi Diao; Yu-Liang Wu (ACM Great Lakes Symposium on VLSI, 2014)

Delete and Correct (DaC): An Atomic Logic Operation for Removing Any Unwanted Wire. - Xing Wei; Tak-Kei Lam; Xiaoqing Yang; Wai-Chung Tang; Yi Diao; Yu-Liang Wu (VLSID, 2014)

A coupling area reduction technique applying ODC shifting. - Yi Diao; Tak-Kei Lam; Xing Wei; Yu-Liang Wu (DATE, 2015)

A universal macro block mapping scheme for arithmetic circuits. - Xing Wei; Yi Diao; Tak-Kei Lam; Yu-Liang Wu (DATE, 2015)

Coupling reverse engineering and SAT to tackle NP-complete arithmetic circuitry verification in ∼O(# of gates). - Yi Diao; Xing Wei; Tak-Kei Lam; Yu-Liang Wu (ASP-DAC, 2016)

To Detect, Locate, and Mask Hardware Trojans in digital circuits by reverse engineering and functional ECO. - Xing Wei; Yi Diao; Yu-Liang Wu (ASP-DAC, 2016)

Motion Resistant Image-Photoplethysmography Based on Spectral Peak Tracking Algorithm. - Bing-Fei Wu; Po-Wei Huang; Chun-Hsien Lin; Meng-Liang Chung; Tsong-Yang Tsou; Yu-Liang Wu (IEEE Access, 2018)

Topological entropy for shifts of finite type over Z and trees. - Jung-Chao Ban; Chih-Hung Chang; Wen-Guei Hu; Yu-Liang Wu (Theor. Comput. Sci., 2022)

NTIRE 2023 Challenge on Efficient Super-Resolution: Methods and Results. - Yawei Li 001; Yulun Zhang 001; Radu Timofte; Luc Van Gool; Lei Yu; Youwei Li; Xinpeng Li 002; Ting Jiang; Qi Wu 017; Mingyan Han; Wenjie Lin; Chengzhi Jiang; et al. (CVPR Workshops, 2023)