A parasitic elimination bootstrapped switch and a fast settling residual amplifier for high-speed and high-resolution pipelined ADC. - Yu Liu 155; Mingliang Chen; Chenge Wang; Jiarui Liu 001; Zhiyu Wang 001; Hua Chen 003; Faxin Yu (IEICE Electron. Express, 2022)

A new extraction method of GaN switch-HEMT small-signal model with capacitance scanning algorithm. - Jiashun Lang; Beibei Lv; Di Zhang; Yu Liu 155; Pengfei Zhang; Jiongjiong Mo; Zhiyu Wang 001; Hua Chen 003; Faxin Yu (IEICE Electron. Express, 2024)

A low-fractional-spur fractional-N PLL using a probability-distribution-shaping delta-sigma modulator. - Yao Yang; Faxin Yu; Haoming Li 004; Jiahao Chen; Tengjia Wang; Yu Liu 155; Hua Chen 003; Jiarui Liu 001 (IEICE Electron. Express, 2025)

A Single-Stage Gain-Boosted Cascode Amplifier With Three-Layer Cascode Feedback Amplifier for Front-End SHA in High-Linearity Pipelined ADC. - Yu Liu 155; Yupeng Shen; Mingliang Chen; Hui Xu; Xubin Chen; Jiarui Liu 001; Zhiyu Wang 001; Faxin Yu (IEEE Trans. Very Large Scale Integr. Syst., 2025)

A 12-bit 10 GS/s Pre-Sampling Pipelined ADC With Split-Capacitor-Based Parasitic Compensation Technique. - Yu Liu 155; Mingliang Chen; Yupeng Shen; Yao Yang; Xubin Chen; Jiarui Liu 001; Zhiyu Wang 001; Faxin Yu (IEEE Trans. Circuits Syst. II Express Briefs, 2026)