Wirebond profiles characterized by a modified linkage-spring model which includes a looping speed factor. - Yu-Lung Lo; Chih-Chiang Tsao (Microelectron. Reliab., 2002)

A mixed-mode delay-locked loop for wide-range operation and multiphase outputs. - Kuo-Hsing Cheng; Yu-Lung Lo; Wen Fang Yu (ISCAS (2), 2003)

A Mixed-Mode Delay-Locked Loop for Wide-Range Operation and Multiphase Clock Generation. - Kuo-Hsing Cheng; Yu-Lung Lo; Wen Fang Yu; Shu-Yin Hung (IWSOC, 2003)

A fast-lock DLL with power-on reset circuit. - Kuo-Hsing Cheng; Yu-Lung Lo (ISCAS (4), 2004)

A fast-lock mixed-mode DLL with wide-range operation and multiphase outputs. - Kuo-Hsing Cheng; Yu-Lung Lo (ESSCIRC, 2005)

A phase-detect synchronous mirror delay for clock skew-compensation circuits. - Kuo-Hsing Cheng; Chen-Lung Wu; Yu-Lung Lo; Chia-Wei Su (ISCAS (2), 2005)

Design of Self-Sampling Based ASK Demodulator for Implantable Microsystem. - Cihun-Siyong Alex Gong; Chen-Lung Wu; Sheng-Yang Ho; Tong-Yi Chen; Jia-Chun Huang; Chia-Wei Su; Chun-Hsien Su; Yin Chang; Kuo-Hsing Cheng; Yu-Lung Lo; Muh-Tian Shiue (ICECS, 2006)

A New Dynamic Floating Input D Flip-Flop (DFIDFF) for High Speed and Ultra Low Voltage Divided-by 4/5 Prescaler. - Ting-Sheng Jau; Wei-Bin Yang; Yu-Lung Lo (ICECS, 2006)

A 100MHz-1GHz adaptive bandwidth phase-locked loop in 90nm process. - Kuo-Hsing Cheng; Kai-Fei Chang; Yu-Lung Lo; Ching-Wen Lai; Yuh-Kuang Tseng (ISCAS, 2006)

A 100 MHz-1 GHz Adaptive Bandwidth PLL Using TDC Technique. - Kuo-Hsing Cheng; Yu-Lung Lo; Ching-Wen Lai; Wei-Bin Yang (ICECS, 2007)

A Phase Interpolator For Sub-1V And High Frequency For Clock And Data Recovery. - Kuo-Hsing Cheng; Pei-Kai Tseng; Yu-Lung Lo (ICECS, 2007)

A Fast-Lock Wide-Range Delay-Locked Loop Using Frequency-Range Selector for Multiphase Clock Generator. - Kuo-Hsing Cheng; Yu-Lung Lo (IEEE Trans. Circuits Syst. II Express Briefs, 2007)

A Spread-Spectrum Clock Generator Using Fractional PLL Controlled Delta-Sigma Modulator for Serial-ATA III. - Kuo-Hsing Cheng; Cheng-Liang Hung; Chih-Hsien Chang; Yu-Lung Lo; Wei-Bin Yang; Jiunn-Way Miaw (DDECS, 2008)

Designing ultra-low voltage PLL Using a bulk-driven technique. - Ting-Sheng Chao; Yu-Lung Lo; Wei-Bin Yang; Kuo-Hsing Cheng (ESSCIRC, 2009)

Vernier Caliper and Equivalent-Signal Sampling for Built-In Jitter Measurement System. - Shu-Yu Jiang; Chan-Wei Huang; Yu-Lung Lo; Kuo-Hsing Cheng (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009)

High-Speed and Ultra-Low-Voltage Divide-by-4/5 Counter for Frequency Synthesizer. - Yu-Lung Lo; Wei-Bin Yang; Ting-Sheng Chao; Kuo-Hsing Cheng (IEICE Trans. Electron., 2009)

Approximate Searching for Music Data in Real-Valued Feature Indexing. - Yu-Lung Lo; Ling-Yi Tsai (J. Convergence Inf. Technol., 2009)

Designing an Ultralow-Voltage Phase-Locked Loop Using a Bulk-Driven Technique. - Yu-Lung Lo; Wei-Bin Yang; Ting-Sheng Chao; Kuo-Hsing Cheng (IEEE Trans. Circuits Syst. II Express Briefs, 2009)

A Pseudo Fractional-N Clock Generator with 50% Duty Cycle Output. - Wei-Bin Yang; Yu-Lung Lo; Ting-Sheng Chao (IEICE Trans. Electron., 2010)

A 0.5-V 0.4-2.24-GHz Inductorless Phase-Locked Loop in a System-on-Chip. - Kuo-Hsing Cheng; Yu-Chang Tsai; Yu-Lung Lo; Jing-Shiuan Huang (IEEE Trans. Circuits Syst. I Regul. Pap., 2011)

A 50 ns Verify Speed in Resistive Random Access Memory by Using a Write Resistance Tracking Circuit. - Shyh-Shyuan Sheu; Kuo-Hsing Cheng; Yu-Sheng Chen; Pang-Shiu Chen; Ming-Jinn Tsai; Yu-Lung Lo (IEICE Trans. Electron., 2012)

A 0.7 V input output-capacitor-free digitally controlled low-dropout regulator with high current efficiency in 0.35 μm CMOS technology. - Yu-Lung Lo; Wei-Jen Chen (Microelectron. J., 2012)

A GHz full-division-range programmable divider with output duty-cycle improved. - Yu-Lung Lo; Jhih-Wei Tsai; Han-Ying Liu; Wei-Bin Yang (DDECS, 2013)

A low-area full-division-range programmable frequency divider with a 50% duty-cycle output. - Yu-Lung Lo; Jhih-Wei Tsai (Microelectron. J., 2013)

Analysis and design considerations of static CMOS logics under process, voltage and temperature variation in UMC 0.18µm CMOS process. - Wei-Bin Yang; Yu-Yao Lin; Chi-Hsiung Wang; Kuo-Ning Chang; Cing-Huan Chen; Yu-Lung Lo (ISPACS, 2015)

A High-Efficiency CMOS Rectifier with Wide Harvesting Range and Wide Band Based on MPPT Technique for Low-Power IoT System Applications. - Yu-Lung Lo; Yi-Hsuan Chuang (Circuits Syst. Signal Process., 2017)

A Low-Voltage PLL Design Using a New Calibration Technique for Low-Power Implantable Biomedical Systems. - Yu-Lung Lo; Wei-Hsiang Ho (Circuits Syst. Signal Process., 2017)

Design of Fast-Locked Digitally Controlled Low-Dropout Regulator for Ultra-low Voltage Input. - Wei-Bin Yang; Yu-Yao Lin; Yu-Lung Lo (Circuits Syst. Signal Process., 2017)

Mueller Optical Coherence Tomophraphy Technique for Non-Invasive Glucose Monitoring. - Tseng-Lin Chen; Quoc-Hung Phan; Yu-Lung Lo (PHOTOPTICS, 2018)

An Intelligent Metrology Architecture With AVM for Metal Additive Manufacturing. - Haw Ching Yang; Muhammad Adnan 004; Chih-Hung Huang; Fan-Tien Cheng; Yu-Lung Lo; Chih-Hua Hsu (IEEE Robotics Autom. Lett., 2019)

An Approach to Measure Tilt Motion, Straightness and Position of Precision Linear Stage with a 3D Sinusoidal-Groove Linear Reflective Grating and Triangular Wave-Based Subdivision Method. - Hsiu-An Tsai; Yu-Lung Lo (Sensors, 2019)

Fiber-Based Triboelectric Nanogenerator for Mechanical Energy Harvesting and Its Application to a Human-Machine Interface. - Chen-Kuei Chung; You-Jun Huang; Tun-Kai Wang; Yu-Lung Lo (Sensors, 2022)

Characterization of Mean Absorbance of Anisotropic Turbid Media Using Stokes-Mueller Matrix Polarimetry Approach. - Chieh-Chen Tsai; Yu-Lung Lo; Ching-Min Chang; Po-Ling Huang (IEEE Trans. Instrum. Meas., 2023)

Intelligent Additive Manufacturing Architecture for Enhancing Uniformity of Surface Roughness and Mechanical Properties of Laser Powder Bed Fusion Components. - Hong-Chuong Tran; Yu-Lung Lo; Haw Ching Yang; Hung-Chang Hsiao; Fan-Tien Cheng; Tsung-Han Kuo (IEEE Trans Autom. Sci. Eng., 2023)

A Low-power PLL with a Standby Mode. - Yu-Chun Hsiao; Rui-Cheng Ai; Zhen-Jie Hong; Yu-Lung Lo; Jen-Chieh Liu (ISOCC, 2024)

A Hierarchical Tree-Structured Control Digital Low Drop-out Regulator with Status-Dumping Mechanism. - Jiann-Chyi Rau; Wei-Bin Yang; Yu-Lung Lo; Chin-Yuan Shih; Cheng-Kai Lin; Che-Chia Chuang (ISOCC, 2024)

A VRO-based TDC with a constant timing resolution ratio between coarse-tuning and fine-tuning stages for a light sensor application. - Jen-Chieh Liu; Jian-Sheng Li; Yanxun Chen; Yu-Lung Lo (Microelectron. J., 2025)