Optimal spacing and capacitance padding for general clock structures. - Yu-Min Lee; Hing Yin Lai; Charlie Chung-Ping Chen (ASP-DAC, 2001)

Hierarchical model order reduction for signal-integrity interconnect synthesis. - Yu-Min Lee; Charlie Chung-Ping Chen (ACM Great Lakes Symposium on VLSI, 2001)

Linear Time Hierarchical Capacitance Extraction without Multipole Expansion. - Saisanthosh Balakrishnan; Jong Hyuk Park; Hyungsuk Kim; Yu-Min Lee; Charlie Chung-Ping Chen (ICCD, 2001)

HiPRIME: hierarchical and passivity reserved interconnect macromodeling engine for RLKC power delivery. - Yahong Cao; Yu-Min Lee; Tsung-Hao Chen; Charlie Chung-Ping Chen (DAC, 2002)

Power grid transient simulation in linear time based on transmission-line-modeling alternating-direction-implicit method. - Yu-Min Lee; Charlie Chung-Ping Chen (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002)

Simultaneous Buffer-sizing and Wire-sizing for Clock Trees Based on Lagrangian Relaxation. - Yu-Min Lee; Charlie Chung-Ping Chen; Yao-Wen Chang; Martin D. F. Wong (VLSI Design, 2002)

A hierarchical analysis methodology for chip-level power delivery with realizable model reduction. - Yu-Min Lee; Charlie Chung-Ping Chen (ASP-DAC, 2003)

The Power Grid Transient Simulation in Linear Time Based on 3D Alternating-Direction-Implicit Method . - Yu-Min Lee; Charlie Chung-Ping Chen (DATE, 2003)

3D thermal-ADI: an efficient chip-level transient thermal simulator. - Ting-Yuan Wang; Yu-Min Lee; Charlie Chung-Ping Chen (ISPD, 2003)

Steady-state thermal characteristics of AMR read/write heads used in tape storage drives. - Icko Eric Timothy Iben; Yu-Min Lee; Wenchien D. Hsiao (IBM J. Res. Dev., 2003)

The power grid transient simulation in linear time based on 3-D alternating-direction-implicit method. - Yu-Min Lee; Charlie Chung-Ping Chen (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003)

HiPRIME: hierarchical and passivity preserved interconnect macromodeling engine for RLKC power delivery. - Yu-Min Lee; Yahong Cao; Tsung-Hao Chen; Janet Meiling Wang; Charlie Chung-Ping Chen (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005)

Simultaneous area minimization and decaps insertion for power delivery network using adjoint sensitivity analysis with IEKS method. - Pei-Yu Huang; Yu-Min Lee; Jeng-Liang Tsai; Charlie Chung-Ping Chen (ISCAS, 2006)

An Aggregation-Based Algebraic Multigrid Method for Power Grid Analysis. - Pei-Yu Huang; Huan-Yu Chou; Yu-Min Lee (ISQED, 2007)

Hierarchical power delivery network analysis using Markov chains. - Pei-Yu Huang; Chih-Kang Lin; Yu-Min Lee (SoCC, 2007)

Timing-constrained yield-driven redundant via insertion. - Jin-Tai Yan; Zhi-Wei Chen; Bo-Yi Chiang; Yu-Min Lee (APCCAS, 2008)

Full-chip thermal analysis for the early design stage via generalized integral transforms. - Pei-Yu Huang; Chih-Kang Lin; Yu-Min Lee (ASP-DAC, 2008)

NGOSS-centric Framework of Telecommunication Electronic Commerce. - Tung-Hsiang Chou; Yu-Min Lee (ISCSCT (2), 2008)

A Process-Oriented System Dynamics Model for Software Development Project Prediction. - Chuen-Lung Chen; Chen-Shu Wang; Ya-Hui Lee; Yu-Min Lee (NCM (2), 2008)

Incomplete Input Inferences on Fuzzy Expert Systems. - Tung-Hsiang Chou; Yu-Min Lee; Ya-Hui Lee (NCM (2), 2008)

Integrating E-services with a Telecommunication E-commerce using Service-Oriented Architecture. - Tung-Hsiang Chou; Yu-Min Lee (J. Softw., 2008)

Stochastic thermal simulation considering spatial correlated within-die process variations. - Pei-Yu Huang; Jia-Hong Wu; Yu-Min Lee (ASP-DAC, 2009)

Post-routing redundant via insertion with wire spreading capability. - Cheok-Kei Lei; Po-Yi Chiang; Yu-Min Lee (ASP-DAC, 2009)

A multiple supply voltage based power reduction method in 3-D ICs considering process variations and thermal effects. - Shih-An Yu; Pei-Yu Huang; Yu-Min Lee (ASP-DAC, 2009)

Full-Chip Thermal Analysis for the Early Design Stage via Generalized Integral Transforms. - Pei-Yu Huang; Yu-Min Lee (IEEE Trans. Very Large Scale Integr. Syst., 2009)

A hierarchical bin-based legalizer for standard-cell designs with minimal disturbance. - Yu-Min Lee; Tsung-You Wu; Po-Yi Chiang (ASP-DAC, 2010)

Statistical electro-thermal analysis with high compatibility of leakage power models. - Huai-Chung Chang; Pei-Yu Huang; Ting-Jung Li; Yu-Min Lee (SoCC, 2010)

Redundant via insertion under timing constraints. - Chi-Wen Pan; Yu-Min Lee (ISQED, 2011)

On-chip statistical hot-spot estimation using mixed-mesh statistical polynomial expression generating and skew-normal based moment matching techniques. - Pei-Yu Huang; Yu-Min Lee; Chi-Wen Pan (ASP-DAC, 2012)

I-LUTSim: An iterative look-up table based thermal simulator for 3-D ICs. - Chi-Wen Pan; Yu-Min Lee; Pei-Yu Huang; Chi-Ping Yang; Chang-Tzu Lin; Chia-Hsin Lee; Yung-Fa Chou; Ding-Ming Kwai (ASP-DAC, 2013)

NUMANA: a hybrid numerical and analytical thermal simulator for 3-D ICs. - Yu-Min Lee; Tsung-Heng Wu; Pei-Yu Huang; Chi-Ping Yang (DATE, 2013)

Power delivery network design for wiring and TSV resource minimization in TSV-based 3-D ICs. - Shu-Han Wei; Yu-Min Lee; Chia-Tung Ho; Chih-Ting Sun; Liang-Chia Cheng (VLSI-DAT, 2013)

An efficient method for analyzing on-chip thermal reliability considering process variations. - Yu-Min Lee; Pei-Yu Huang (ACM Trans. Design Autom. Electr. Syst., 2013)

Incremental transient simulation of power grid. - Chia-Tung Ho; Yu-Min Lee; Shu-Han Wei; Liang-Chia Cheng (ISPD, 2014)

A TSV noise-aware 3-D placer. - Yu-Min Lee; Chun Chen; JiaXing Song; Kuan-Te Pan (DATE, 2015)

LUTSim: A Look-Up Table-Based Thermal Simulator for 3-D ICs. - Yu-Min Lee; Chi-Wen Pan; Pei-Yu Huang; Chi-Ping Yang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015)

Yield-driven redundant power bump assignment for power network robustness. - Yu-Min Lee; Chi-Han Lee; Yan-Cheng Zhu (ASP-DAC, 2017)

Thermal modeling and design on smartphones with heat pipe cooling technique. - Hong-Wen Chiou; Yu-Min Lee; Hsuan-Hsuan Hsiao; Liang-Chia Cheng (ICCAD, 2017)

InTraSim: Incremental Transient Simulation of Power Grids. - Yu-Min Lee; Chia-Tung Ho (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017)

NaPer: A TSV Noise-Aware Placer. - Yu-Min Lee; Kuan-Te Pan; Chun Chen (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Phone-nomenon: a system-level thermal simulator for handheld devices. - Hong-Wen Chiou; Yu-Min Lee; Shin-Yu Shiau; Chi-Wen Pan; Tai-Yu Chen (ASP-DAC, 2019)

Multi-angle bended heat pipe design using x-architecture routing with dynamic thermal weight on mobile devices. - Hsuan-Hsuan Hsiao; Hong-Wen Chiou; Yu-Min Lee (ASP-DAC, 2019)

XGBIR: An XGBoost-based IR Drop Predictor for Power Delivery Network. - Chi-Hsien Pao; An-Yu Su; Yu-Min Lee (DATE, 2020)

Thermal Pad Design Flow for Automotive Electronics. - Guan-Jia Chen; Hong-Wen Chiou; Yu-Teng Chang; Yu-Min Lee (ICCE-TW, 2021)

Chiplet Placement for 2.5D IC with Sequence Pair Based Tree and Thermal Consideration. - Hong-Wen Chiou; Jia-Hao Jiang; Yu-Teng Chang; Yu-Min Lee; Chi-Wen Pan (ASP-DAC, 2023)

Phone-nomenon 2.0: A compact thermal model for smartphones. - Yu-Min Lee; Hong-Wen Chiou; Shin-Yu Shiau; Chi-Wen Pan; Shih-Ting Lin (IET Comput. Digit. Tech., 2023)

SpotLight: A Hotspot-Greedy, Light-Weighted, and Automated Thermal Modeling Framework for Early Smartphone Design. - Chin-Wei Wu; Yu-Min Lee; Pei-Yu Huang; Bo-Jiun Yang; Tai-Yu Chen; Ting-Chang Huang; Yen-Lin Lee (ISQED, 2024)

Therunet-SP: 2.5D IC Thermal Simulation Using U-Net Convolution and Scaling Procedure. - Yu-Min Lee; Shun-Ping Huang; Ying-Hui Lin (ISQED, 2025)

MErBAG: Mesh Error Based Adaptive Grid Generation in System-Level Thermal Analysis. - Yu-Min Lee; Shih-Chieh Hsu; Bo-Yi Tsai; Zong-Lin Lu (ISQED, 2025)

Thermal Model Extraction at Chip Boundaries for Thermal Simulation of Chip in a System. - Kai-Xiang Lin; Yu-Min Lee; Bo-Yi Tsai (ISQED, 2025)