A 40Gb/s TX and RX chip set in 65nm CMOS. - Ming-Shuan Chen; Yu-Nan Shih; Chen-Lun Lin; Hao-Wei Hung; Jri Lee (ISSCC, 2011)

A Fully-Integrated 40-Gb/s Transceiver in 65-nm CMOS Technology. - Ming-Shuan Chen; Yu-Nan Shih; Chen-Lun Lin; Hao-Wei Hung; Jri Lee (IEEE J. Solid State Circuits, 2012)

A 56Gb/s PAM-4 Receiver with Voltage Pre-Shift CTLE and 10-Tap DFE of Tap-1 Speculation in 7nm FinFET. - Wei-Chih Chen; Shu-Chun Yang; Yu-Nan Shih; Wen-Hung Huang; Chien-Chun Tsai; Kenny Cheng-Hsiang Hsieh (VLSI Circuits, 2019)