Extraction Error Diagnosis and Correction in High-Performance Designs. - Yu-Shen Yang; Jiang Brandon Liu; Paul J. Thadikaran; Andreas G. Veneris (ITC, 2003)

Extraction Error Analysis, Diagnosis and Correction in Custom-Made High-Performance Designs. - Yu-Shen Yang; Jiang Brandon Liu; Paul J. Thadikaran; Andreas G. Veneris (MTV, 2003)

Extraction Error Modeling and Automated Model Debugging in High-Performance Low Power Custom Designs. - Yu-Shen Yang; Andreas G. Veneris; Paul J. Thadikaran; Srikanth Venkataraman (DATE, 2005)

Seamless Integration of SER in Rewiring-Based Design Space Exploration. - Sobeeh Almukhaizim; Yiorgos Makris; Yu-Shen Yang; Andreas G. Veneris (ITC, 2006)

Extraction error modeling and automated model debugging in high-performance custom designs. - Yu-Shen Yang; Andreas G. Veneris; Paul J. Thadikaran; Srikanth Venkataraman (IEEE Trans. Very Large Scale Integr. Syst., 2006)

Automating Logic Rectification by Approximate SPFDs. - Yu-Shen Yang; Subarnarekha Sinha; Andreas G. Veneris; Robert K. Brayton (ASP-DAC, 2007)

On the Minimization of Potential Transient Errors and SER in Logic Circuits Using SPFD. - Sobeeh Almukhaizim; Yiorgos Makris; Yu-Shen Yang; Andreas G. Veneris (IOLTS, 2008)

Automated data analysis solutions to silicon debug. - Yu-Shen Yang; Nicola Nicolici; Andreas G. Veneris (DATE, 2009)

Sequential logic rectifications with approximate SPFDs. - Yu-Shen Yang; Subarna Sinha; Andreas G. Veneris; Robert K. Brayton; Duncan Exon Smith (DATE, 2009)

Automated silicon debug data analysis techniques for a hardware data acquisition environment. - Yu-Shen Yang; Brian Keng; Nicola Nicolici; Andreas G. Veneris; Sean Safarpour (ISQED, 2010)

Automating Logic Transformations With Approximate SPFDs. - Yu-Shen Yang; Subarna Sinha; Andreas G. Veneris; Robert K. Brayton (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011)

Automated data analysis techniques for a modern silicon debug environment. - Yu-Shen Yang; Andreas G. Veneris; Nicola Nicolici; Masahiro Fujita (ASP-DAC, 2012)

Leveraging reconfigurability to raise productivity in FPGA functional debug. - Zissis Poulos; Yu-Shen Yang; Jason Helge Anderson; Andreas G. Veneris; Bao Le (DATE, 2012)

Automating Data Analysis and Acquisition Setup in a Silicon Debug Environment. - Yu-Shen Yang; Andreas G. Veneris; Nicola Nicolici (IEEE Trans. Very Large Scale Integr. Syst., 2012)

A failure triage engine based on error trace signature extraction. - Zissis Poulos; Yu-Shen Yang; Andreas G. Veneris (IOLTS, 2013)

Simulation and satisfiability guided counter-example triage for RTL design debugging. - Zissis Poulos; Yu-Shen Yang; Andreas G. Veneris; Bao Le (ISQED, 2014)