An Efficient Mechanism for Performance Optimization of Variable-Latency Designs. - Yu-Shih Su; Da-Chung Wang; Shih-Chieh Chang; Malgorzata Marek-Sadowska (DAC, 2007)

Synthesis of a novel timing-error detection architecture. - Yu-Shih Su; Po-Hsien Chang; Shih-Chieh Chang; TingTing Hwang (ACM Trans. Design Autom. Electr. Syst., 2008)

Value assignment of adjustable delay buffers for clock skew minimization in multi-voltage mode designs. - Yu-Shih Su; Wing-Kai Hon; Cheng-Chih Yang; Shih-Chieh Chang; Yeong-Jar Chang (ICCAD, 2009)

Clock Skew Minimization in Multi-Voltage Mode Designs Using Adjustable Delay Buffers. - Yu-Shih Su; Wing-Kai Hon; Cheng-Chih Yang; Shih-Chieh Chang; Yeong-Jar Chang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010)

Fault-tolerant 3D clock network. - Chiao-Ling Lung; Yu-Shih Su; Shih-Hsiu Huang; Yiyu Shi 001; Shih-Chieh Chang (DAC, 2011)

Performance Optimization Using Variable-Latency Design Style. - Yu-Shih Su; Da-Chung Wang; Shih-Chieh Chang; Malgorzata Marek-Sadowska (IEEE Trans. Very Large Scale Integr. Syst., 2011)

Capturing the phantom of the power grid - on the runtime adaptive techniques for noise reduction. - Tao Wang; Pei-Wen Luo; Yu-Shih Su; Liang-Chia Cheng; Ding-Ming Kwai; Yiyu Shi 001 (ASP-DAC, 2012)

Benchmarking for research in power delivery networks of three-dimensional integrated circuits. - Pei-Wen Luo; Chun Zhang; Yung-Tai Chang; Liang-Chia Cheng; Hung-Hsie Lee; Bih-Lan Sheu; Yu-Shih Su; Ding-Ming Kwai; Yiyu Shi 001 (ISPD, 2013)

Through-Silicon Via Fault-Tolerant Clock Networks for 3-D ICs. - Chiao-Ling Lung; Yu-Shih Su; Hsih-Hsiu Huang; Yiyu Shi 001; Shih-Chieh Chang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013)