A 10 GHz Dual-Loop PLL with Active Noise Cancellation Achieving 12dB Spur and 29% Noise Reduction. - Yu-Sian Lu; Cheng-Lung Lee; Wei-Zen Chen (A-SSCC, 2021)

A 10 GHz Dual-Loop PLL With Active Cycle-Jitter Correction Achieving 12dB Spur and 29% Jitter Reduction. - Yu-Ping Huang; Yu-Sian Lu; Wei-Zen Chen (IEEE Open J. Circuits Syst., 2024)