Methodology of generating dual-cell-aware tests. - Yu-Hao Huang; Ching-Ho Lu; Tse-Wei Wu; Yu-Teng Nien; Ying-Yen Chen; Max Wu; Jih-Nung Lee; Mango C.-T. Chao (VTS, 2017)

Methodology of Generating Timing-Slack-Based Cell-Aware Tests. - Yu-Teng Nien; Kai-Chiang Wu; Dong-Zhen Lee; Ying-Yen Chen; Po-Lin Chen; Mason Chern; Jih-Nung Lee; Shu-Yi Kao; Mango Chia-Tso Chao (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Test Methodology for Defect-Based Bridge Faults. - Shuo-Wen Chang; Yu-Teng Nien; Yu-Pang Hu; Kai-Chiang Wu; Chi Chun Wang; Fu-Sheng Huang; Yi-Lun Tang; Yung-Chen Chen; Ming-Chien Chen; Mango C.-T. Chao (IEEE Trans. Very Large Scale Integr. Syst., 2022)

Test Generation for Defect-Based Faults of Scan Flip-Flops. - Yu-Teng Nien; Chen-Hong Li; Pei-Yin Wu; Yung-Jheng Wang; Kai-Chiang Wu; Mango C.-T. Chao (VTS, 2023)

Test Methodology for Detecting Defect-Based Hold-Time Faults. - Cheng-Hsiang Tsai; Yu-Teng Nien; Guan-You Chen; Mango Chia-Tso Chao (VTS, 2025)