Anti-ESD impacts on 60-V P-channel LDMOS devices as none-ODs zone inserting in the bulk region. - Shen-Li Chen; Shawn Chang; Yu-Ting Huang 007; Shun-Bao Chang (ICCE-TW, 2015)

ESD reliability building in 0.25 μm 60-V p-channel LDMOS DUTs with different embedded SCRs. - Shen-Li Chen; Yu-Ting Huang 007; Shawn Chang; Shun-Bao Chang (ICCE-TW, 2015)

ESD protection design for the 45-V pLDMOS-SCR (p-n-p-arranged) devices with source-discrete distributions. - Shen-Li Chen; Yu-Ting Huang 007; Chih-Ying Yen; Kuei-Jyun Chen; Yi-Cih Wu; Jia-Ming Lin; Chih-Hung Yang (GCCE, 2016)

Design of High-ESD Reliability in HV Power pLDMOS Transistors by the Drain-Side Isolated SCRs. - Shen-Li Chen; Yu-Ting Huang 007; Yi-Cih Wu (IEICE Trans. Electron., 2017)

Design and Impact on ESD/LU Immunities by Drain-Side Super-Junction Structures in Low-(High-)Voltage MOSFETs for the Power Applications. - Shen-Li Chen; Yu-Ting Huang 007; Shawn Chang (IEICE Trans. Electron., 2018)