Failure Factor Based Yield Enhancement for SRAM Designs. - Yu-Tsao Hsing; Chih-Wea Wang; Ching-Wei Wu; Chih-Tsun Huang; Cheng-Wen Wu (DFT, 2004)

Fault-Pattern Oriented Defect Diagnosis for Flash Memory. - Mu-Hsien Hsu; Yu-Tsao Hsing; Jen-Chieh Yeh; Cheng-Wen Wu (MTDT, 2006)

SDRAM Delay Fault Modeling and Performance Testing. - Yu-Tsao Hsing; Chun-Chieh Huang; Jen-Chieh Yeh; Cheng-Wen Wu (VTS, 2007)

An Adaptive-Rate Error Correction Scheme for NAND Flash Memory. - Te-Hsuan Chen; Yu-Ying Hsiao; Yu-Tsao Hsing; Cheng-Wen Wu (VTS, 2009)

Hybrid BIST Scheme for Multiple Heterogeneous Embedded Memories. - Li-Ming Denq; Yu-Tsao Hsing; Cheng-Wen Wu (IEEE Des. Test Comput., 2009)

Economic Analysis of the HOY Wireless Test Methodology. - Yu-Tsao Hsing; Li-Ming Denq; Chao-Hsun Chen; Cheng-Wen Wu (IEEE Des. Test Comput., 2010)

SOC Test Architecture and Method for 3-D ICs. - Chih-Yen Lo; Yu-Tsao Hsing; Li-Ming Denq; Cheng-Wen Wu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010)

3D-IC BISR for stacked memories using cross-die spares. - Chun-Chuan Chi; Yung-Fa Chou; Ding-Ming Kwai; Yu-Ying Hsiao; Cheng-Wen Wu; Yu-Tsao Hsing; Li-Ming Denq; Tsung-Hsiang Lin (VLSI-DAT, 2012)