A practical load-optimized VCO design for low-jitter 5 V 500 MHz digital phase-locked loop. - Chua-Chin Wang; Yu-Tsun Chien; Ying-Pei Chen (ISCAS (2), 1999)

Design of an inter-plane circuit for clocked PLAs. - Chua-Chin Wang; Yu-Tsun Chien; Ying-Pei Chen (ISCAS, 2000)

A Practical Load-optimized VCO Design for Low-jitter 5V 500 MHz Digital Phase-locked Loop. - Chua-Chin Wang; Yu-Tsun Chien; Ying-Pei Chen (VLSI Design, 2000)

Pattern Recognitin by High-Capacity Polynomial Bidirectional Hetero-Associative Network. - Chua-Chin Wang; Cheng-Fa Tsai; Yu-Tsun Chien (J. Inf. Sci. Eng., 2001)

Design of an Inter-plane Circuit for Clocked PLAs. - Chua-Chin Wang; Ya-Hsin Hsueh; Yu-Tsun Chien; Ying-Pei Chen (VLSI Design, 2002)

Designer-Driven Topology Optimization for Pipelined Analog to Digital Converters. - Yu-Tsun Chien; Dong Chen; Jea-Hong Lou; Gin-Kou Ma; Rob A. Rutenbar; Tamal Mukherjee (DATE, 2005)