A clock interpolation structure using DLL for clock distribution in ADC. - Shijia Zhu; Yu Wang 167; Fan Ye 001; Jun Xu (ASICON, 2017)

A Scalable FPGA Engine for Parallel Acceleration of Singular Value Decomposition. - Yu Wang 167; Jeong-Jun Lee; Yu Ding 005; Peng Li 001 (ISQED, 2020)

Algorithm and Hardware Co-Design for FPGA Acceleration of Hamiltonian Monte Carlo Based No-U-Turn Sampler. - Yu Wang 167; Peng Li 001 (ASAP, 2021)

AutoNF: Automated Architecture Optimization of Normalizing Flows with Unconstrained Continuous Relaxation Admitting Optimal Discrete Solution. - Yu Wang 167; Ján Drgona; Jiaxin Zhang 005; Karthik Somayaji Nanjangud Suryanarayana; Malachi Schram; Frank Liu 001; Peng Li 001 (AAAI, 2023)

Contrastive Learning with Consistent Representations. - Zihu Wang; Yu Wang 167; Hanbin Hu; Peng Li 001 (CoRR, 2023)

Semi-supervised Learning of Dynamical Systems with Neural Ordinary Differential Equations: A Teacher-Student Model Approach. - Yu Wang 167; Yuxuan Yin; Karthik Somayaji N. S.; Ján Drgona; Malachi Schram; Mahantesh Halappanavar; Frank Liu 001; Peng Li 001 (AAAI, 2024)

ADO-LLM: Analog Design Bayesian Optimization with In-Context Learning of Large Language Models. - Yuxuan Yin; Yu Wang 167; Boxun Xu; Peng Li 001 (ICCAD, 2024)

High-Dimensional Bayesian Optimization via Semi-Supervised Learning with Optimized Unlabeled Data Sampling. - Yuxuan Yin; Yu Wang 167; Peng Li 001 (ICML, 2024)

Towards the Mitigation of Confirmation Bias in Semi-supervised Learning: a Debiased Training Perspective. - Yu Wang 167; Yuxuan Yin; Peng Li 001 (CoRR, 2024)

Extreme Risk Mitigation in Reinforcement Learning using Extreme Value Theory. - Karthik Somayaji N. S.; Yu Wang 167; Malachi Schram; Ján Drgona; Mahantesh M. Halappanavar; Frank Liu 001; Peng Li 001 (Trans. Mach. Learn. Res., 2024)

Contrastive Learning with Consistent Representations. - Zihu Wang; Yu Wang 167; Zhuotong Chen; Hanbin Hu; Peng Li 001 (Trans. Mach. Learn. Res., 2024)