Combining technology mapping and placement for delay-optimization in FPGA designs. - Chau-Shen Chen; Yu-Wen Tsay; TingTing Hwang; Allen C.-H. Wu; Youn-Long Lin (ICCAD, 1993)

Combining technology mapping and placement for delay-minimization in FPGA designs. - Chau-Shen Chen; Yu-Wen Tsay; TingTing Hwang; Allen C.-H. Wu; Youn-Long Lin (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995)

A row-based cell placement method that utilizes circuit structural properties. - Yu-Wen Tsay; Youn-Long Lin (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995)

Preserving HDL synthesis hierarchy for cell placement. - Yu-Wen Tsay; Wen-Jong Fang; Allen C.-H. Wu; Youn-Long Lin (ISPD, 1997)

Integrating logic retiming and register placement. - Tzu-Chieh Tien; Hsiao-Pin Su; Yu-Wen Tsay; Yih-Chih Chou; Youn-Long Lin (ICCAD, 1998)