A 1.2 V CMOS multiplier using low-power current-sensing complementary pass-transistor logic. - Kuo-Hsing Cheng; Yu-Yee Liow (ICECS, 1996)

A new dynamic ternary sense amplifier for 1.5-bit/cell multi-level low-voltage CMOS DRAMs. - Chung-Yu Wu; Yu-Yee Liow (ISCAS (1), 1999)

High-speed CMOS current-mode wave-pipelined analog-to-digital converter. - Chung-Yu Wu; Yu-Yee Liow (ICECS, 2000)

The design of high-speed pipelined analog-to-digital converters using voltage-mode sampling and current mode processing techniques. - Yu-Yee Liow; Chung-Yu Wu (ISCAS (3), 2002)

New current-mode wave-pipelined architectures for high-speed analog-to-digital converters. - Chung-Yu Wu; Yu-Yee Liow (IEEE Trans. Circuits Syst. I Regul. Pap., 2004)