Sequential equivalence checking of clock-gated circuits. - Yu-Yun Dai; Kei-Yong Khoo; Robert K. Brayton (DAC, 2015)

Circuit recognition with deep learning. - Yu-Yun Dai; Robert K. Brayton (HOST, 2017)

Verification and Synthesis of Clock-Gated Circuits. - Yu-Yun Dai (2017)

Identifying Transparent Logic in Gate-Level Circuits. - Yu-Yun Dai; Robert K. Brayton (Advanced Logic Synthesis, 2018)

Verification and Synthesis of Clock-Gated Circuits. - Yu-Yun Dai; Robert K. Brayton (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019)