A 12.6MW 573-2, 901KS/S Reconfigurable Processor for Reconstruction of Compressively-Sensed Phvsiological Signals. - Yu-Zhe Wang; Yao-Pin Wang; Yi-Chung Wu; Chia-Hsiang Yang (VLSI Circuits, 2018)

Micro-Architecture Optimization for Low-Power Bitcoin Mining ASICs. - Yu-Zhe Wang; Jingjie Wu; Shi-Hao Chen; Mango Chia-Tso Chao; Chia-Hsiang Yang (VLSI-DAT, 2019)

A 12.6 mW, 573-2901 kS/s Reconfigurable Processor for Reconstruction of Compressively Sensed Physiological Signals. - Yu-Zhe Wang; Yao-Pin Wang; Yi-Chung Wu; Chia-Hsiang Yang (IEEE J. Solid State Circuits, 2019)