DrowsyNet: Convolutional neural networks with runtime power-accuracy tunability using inference-stage dropout. - Ren-Shuo Liu; Yun-Chen Lo; Yuan-Chun Luo; Chih-Yu Shen; Cheng-Ju Lee (VLSI-DAT, 2018)

Modeling Multi-states in Ferroelectric Tunnel Junction. - Yuan-Chun Luo; Jae Hur; Panni Wang; Asif Islam Khan; Shimeng Yu (DRC, 2020)

A FeRAM based Volatile/Non-volatile Dual-mode Buffer Memory for Deep Neural Network Training. - Yandong Luo; Yuan-Chun Luo; Shimeng Yu (DATE, 2021)

Compute-in-Memory: From Device Innovation to 3D System Integration. - Shimeng Yu; Wonbo Shim; Jae Hur; Yuan-chun Luo; Gihun Choe; Wantong Li; Anni Lu; Xiaochen Peng (ESSDERC, 2021)

A Technology Path for Scaling Embedded FeRAM to 28nm with 2T1C Structure. - Jae Hur; Yuan-Chun Luo; Zheng Wang; Wonbo Shim; Asif Islam Khan; Shimeng Yu (IMW, 2021)

Design of Non-volatile Capacitive Crossbar Array for In-Memory Computing. - Yuan-Chun Luo; Anni Lu; Jae Hur; Shaolan Li; Shimeng Yu (IMW, 2021)

Nonvolatile Capacitive Crossbar Array for In-Memory Computing. - Jae Hur; Yuan-Chun Luo; Anni Lu; Tzu-Han Wang; Shaolan Li; Asif Islam Khan; Shimeng Yu (Adv. Intell. Syst., 2022)

A Ferroelectric-Based Volatile/Non-Volatile Dual-Mode Buffer Memory for Deep Neural Network Accelerators. - Yandong Luo; Yuan-Chun Luo; Shimeng Yu (IEEE Trans. Computers, 2022)

Design and Optimization of Non-Volatile Capacitive Crossbar Array for In-Memory Computing. - Yuan-Chun Luo; Anni Lu; Jae Hur; Shaolan Li; Shimeng Yu (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

Low-Frequency Noise Characteristics of Ferroelectric Field-Effect Transistors. - Omkar Phadke; Khandker Akif Aabrar; Yuan-chun Luo; Sharadindu Gopal Kirtania; Asif Islam Khan; Suman Datta; Shimeng Yu (IRPS, 2023)

Scalable In-Memory Clustered Annealer With Temporal Noise of Charge Trap Transistor for Large Scale Travelling Salesman Problems. - Anni Lu; Jae Hur; Yuan-Chun Luo; Hai Li 008; Dmitri E. Nikonov; Ian A. Young; Yang-Kyu Choi; Shimeng Yu (IEEE J. Emerg. Sel. Topics Circuits Syst., 2023)

A Cross-layer Framework for Design Space and Variation Analysis of Non-Volatile Ferroelectric Capacitor-Based Compute-in-Memory Accelerators. - Yuan-Chun Luo; James Read; Anni Lu; Shimeng Yu (ASPDAC, 2024)

Digital CIM with Noisy SRAM Bit: A Compact Clustered Annealer for Large-Scale Combinatorial Optimization. - Anni Lu; Junmo Lee; Yuan-Chun Luo; Hai Li 008; Ian A. Young; Shimeng Yu (DAC, 2024)

Engineering nvCap From FEOL to BEOL with Ferroelectric Small-signal Non-destructive Read. - Tae-Hyeon Kim; Yuan-Chun Luo; Omkar Phadke; James Read; Shimeng Yu (IMW, 2024)

Endurance-Aware Compiler for 3-D Stackable FeRAM as Global Buffer in TPU-Like Architecture. - Yuan-Chun Luo; Anni Lu; Yandong Luo; Sou-Chi Chang; Uygar Avci; Shimeng Yu (IEEE Trans. Very Large Scale Integr. Syst., 2024)

Thermally Constrained Codesign of Heterogeneous 3-D Integration of Compute-in-Memory, Digital ML Accelerator, and RISC-V Cores for Mixed ML and Non-ML Workloads. - Yuan-Chun Luo; Anni Lu; Janak Sharda; Moritz Scherer 001; Jorge Tomás Gómez; Syed Shakib Sarwar; Ziyun Li; Reid Frederick Pinkham; Barbara De Salvo; Shimeng Yu (IEEE Trans. Very Large Scale Integr. Syst., 2024)

Digital Compute-in-Memory Ising Annealer with Ferroelectric Capacitor-Based nvSRAM for Combinatorial Optimization Problems. - Yuyao Kong; Jianwei Jia; Anni Lu; Faaiq G. Waqar; Yuan-Chun Luo; Hai Li 001; Ian A. Young; Shimeng Yu (ISCAS, 2025)

NeuroSim V1.5: Improved Software Backbone for Benchmarking Compute-in-Memory Accelerators with Device and Circuit-level Non-idealities. - James Read; Ming-Yen Lee; Wei-Hsing Huang; Yuan-Chun Luo; Anni Lu; Shimeng Yu (CoRR, 2025)