Geography-aware active data dissemination in mobile social networks. - Jialu Fan; Yuan Du; Wei Gao 006; Jiming Chen 001; Youxian Sun (MASS, 2010)

Tilt & touch: mobile phone for 3D interaction. - Yuan Du; Haoyi Ren; Gang Pan 001; Shijian Li (UbiComp, 2011)

Broadcast yourself: understanding YouTube uploaders. - Yuan Ding 003; Yuan Du; Yingkai Hu; Zhengye Liu; Luqin Wang; Keith W. Ross; Anindya Ghose (Internet Measurement Conference, 2011)

Experimental analysis of user mobility pattern in mobile social networks. - Yuan Du; Jialu Fan; Jiming Chen 001 (WCNC, 2011)

DelQue: A Socially Aware Delegation Query Scheme in Delay-Tolerant Networks. - Jialu Fan; Jiming Chen 001; Yuan Du; Ping Wang; Youxian Sun (IEEE Trans. Veh. Technol., 2011)

ConSub: Incentive-Based Content Subscribing in Selfish Opportunistic Mobile Networks. - Huan Zhou 002; Jiming Chen 001; Jialu Fan; Yuan Du; Sajal K. Das 001 (IEEE J. Sel. Areas Commun., 2013)

Geocommunity-Based Broadcasting for Data Dissemination in Mobile Social Networks. - Jialu Fan; Jiming Chen 001; Yuan Du; Wei Gao 006; Jie Wu 001; Youxian Sun (IEEE Trans. Parallel Distributed Syst., 2013)

Aspectual Properties of Conversational Activities. - Rebecca J. Passonneau; Boxuan Guan; Cho Ho Yeung; Yuan Du; Emma Conner (SIGDIAL Conference, 2014)

A 5.4-mW 4-Gb/s 5-band QPSK transceiver for frequency-division multiplexing memory interface. - Wei-Han Cho; Yilei Li; Yanghyo Kim; Po-Tsang Huang; Yuan Du; Sheau Jiung Lee; Mau-Chung Frank Chang (CICC, 2015)

10.2 A 38mW 40Gb/s 4-lane tri-band PAM-4 / 16-QAM transceiver in 28nm CMOS for high-speed Memory interface. - Wei-Han Cho; Yilei Li; Yuan Du; Chien-Heng Wong; Jieqiong Du; Po-Tsang Huang; Sheau Jiung Lee; Huan-Neng Ron Chen; Chewnpu Jou; Fu-Lung Hsueh; Mau-Chung Frank Chang (ISSCC, 2016)

A 16Gb/s 14.7mW tri-band cognitive serial link transmitter with forwarded clock to enable PAM-16 / 256-QAM and channel response detection in 28 nm CMOS. - Yuan Du; Wei-Han Cho; Yilei Li; Chien-Heng Wong; Jieqiong Du; Po-Tsang Huang; Yanghyo Kim; Zuow-Zun Chen; Sheau Jiung Lee; Mau-Chung Frank Chang (VLSI Circuits, 2016)

A 0.56 THz Phase-Locked Frequency Synthesizer in 65 nm CMOS Technology. - Yan Zhao 002; Zuow-Zun Chen; Yuan Du; Yilei Li; Richard Al Hadi; Gabriel Virbila; Yinuo Xu; Yanghyo Kim; Adrian Tang 002; Theodore Reck; Mau-Chung Frank Chang (IEEE J. Solid State Circuits, 2016)

Cognitive Serial Interface with Multi-Band Signaling and Channel Learning Mechanism. - Yuan Du (2016)

A Reconfigurable Streaming Deep Convolutional Neural Network Accelerator for Internet of Things. - Li Du; Yuan Du; Yilei Li; Mau-Chung Frank Chang (CoRR, 2017)

A Streaming Accelerator for Deep Convolutional Neural Networks with Image and Feature Decomposition for Resource-limited System Applications. - Yuan Du; Li Du; Yilei Li; Junjie Su; Mau-Chung Frank Chang (CoRR, 2017)

A Memristive Neural Network Computing Engine using CMOS-Compatible Charge-Trap-Transistor (CTT). - Yuan Du; Li Du; Xuefeng Gu; Xiao Wang; Mau-Chung Frank Chang (CoRR, 2017)

Multi-core architecture with asynchronous clocks to prevent power analysis attacks. - Yuan Du; Yong Ye; Weiliang Jing; Zhenhua Li; Xiaoyun Li; Zhitang Song; Bomy Chen (IEICE Electron. Express, 2017)

Logic area reduction using the deep trench isolation technique based on 40 nm embedded PCM process. - Yuan Du; Yong Ye; Weiliang Jing; Xiaoyun Li; Zhitang Song; Bomy Chen (IEICE Electron. Express, 2017)

CAM-based retention-aware DRAM (CRA-DRAM) for refresh power reduction. - Yong Ye; Yuan Du; Weiliang Jing; Xiaoyun Li; Zhitang Song; Bomy Chen (IEICE Electron. Express, 2017)

Erratum: CAM-based retention-aware DRAM (CRA-DRAM) for refresh power reduction [IEICE Electronics Express Vol. 14 (2017) No. 10 pp. 20170053]. - Yong Ye; Yuan Du; Weiliang Jing; Xiaoyun Li; Zhitang Song; Bomy Chen (IEICE Electron. Express, 2017)

A 16-Gb/s 14.7-mW Tri-Band Cognitive Serial Link Transmitter With Forwarded Clock to Enable PAM-16/256-QAM and Channel Response Detection. - Yuan Du; Wei-Han Cho; Po-Tsang Huang; Yilei Li; Chien-Heng Wong; Jieqiong Du; Yanghyo Kim; Boyu Hu; Li Du; Chun-Chen Liu; Sheau Jiung Lee; Mau-Chung Frank Chang (IEEE J. Solid State Circuits, 2017)

Retention-Aware Hybrid Main Memory (RAHMM): Big DRAM and Little SCM. - Weiliang Jing; Kai Yang; Yinyin Lin; Beomseop Lee; Sangkyu Yoon; Yong Ye; Yuan Du; Bomy Chen (IEEE Trans. Computers, 2017)

A Capacitor-DAC-Based Technique For Pre-Emphasis-Enabled Multilevel Transmitters. - Boyu Hu; Yuan Du; Rulin Huang; Jeffrey Lee; Young-Kai Chen; Mau-Chung Frank Chang (IEEE Trans. Circuits Syst. II Express Briefs, 2017)

An R2R-DAC-Based Architecture for Equalization-Equipped Voltage-Mode PAM-4 Wireline Transmitter Design. - Boyu Hu; Yuan Du; Rulin Huang; Jeffrey Lee; Young-Kai Chen; Mau-Chung Frank Chang (IEEE Trans. Very Large Scale Integr. Syst., 2017)

A fully integrated 28nm CMOS dual source adaptive thermoelectric and RF energy harvesting circuit with 110mv startup voltage. - Yiwu Tang; Chien-Heng Wong; Yuan Du; Li Du; Yilei Li; Mau-Chung Frank Chang (CICC, 2018)

A 20Gb/s 79.5mW 127GHz CMOS transceiver with digitally pre-distorted PAM-4 modulation for contactless communications. - Yanghyo Kim; Boyu Hu; Yuan Du; Adrian Tang 002; Huan-Neng Ron Chen; Chewnpu Jou; Jason Cong; Tatsuo Itoh; Mau-Chung Frank Chang (ISSCC, 2018)

A New Azimuth-Dependent Elevation Weight (ADEW) Model for Real-Time Deformation Monitoring in Complex Environment by Multi-GNSS. - Junqiang Han; Guanwen Huang; Qin Zhang 010; Rui Tu; Yuan Du; Xiaolei Wang (Sensors, 2018)

A Single Layer 3-D Touch Sensing System for Mobile Devices Application. - Li Du; Chun-Chen Liu; Yan Zhang 050; Yilei Li; Yuan Du; Yen-Cheng Kuan; Mau-Chung Frank Chang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

A Novel Fully Synthesizable All-Digital RF Transmitter for IoT Applications. - Yilei Li; Kirti Dhwaj; Chien-Heng Wong; Yuan Du; Li Du; Yiwu Tang; Yiyu Shi 001; Tatsuo Itoh; Mau-Chung Frank Chang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

A Reconfigurable Streaming Deep Convolutional Neural Network Accelerator for Internet of Things. - Li Du; Yuan Du; Yilei Li; Junjie Su; Yen-Cheng Kuan; Chun-Chen Liu; Mau-Chung Frank Chang (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

A 2-GS/s 8-Bit ADC Featuring Virtual-Ground Sampling Interleaved Architecture in 28-nm CMOS. - X. Shawn Wang; Xin Jin; Jieqiong Du; Yilei Li; Yuan Du; Chien-Heng Wong; Yen-Cheng Kuan; Chi-Hang Chan; Mau-Chung Frank Chang (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

A 7.5-mW 10-Gb/s 16-QAM wireline transceiver with carrier synchronization and threshold calibration for mobile inter-chip communications in 16-nm FinFET. - Jieqiong Du; Chien-Heng Wong; Yo-Hao Tu; Wei-Han Cho; Yilei Li; Yuan Du; Po-Tsang Huang; Sheau Jiung Lee; Mau-Chung Frank Chang (NOCS, 2019)

Subsystem under 3D-Storage Class Memory on a chip. - Jipeng Guo 002; Haibo Wang; Weiliang Jing; Haixin Li; Yuan Du; Zhitang Song; Bomy Chen (Comput. Electr. Eng., 2019)

A Millimeter-Wave CMOS Transceiver With Digitally Pre-Distorted PAM-4 Modulation for Contactless Communications. - Yanghyo Rod Kim; Boyu Hu; Yuan Du; Wei-Han Cho; Rulin Huang; Adrian Tang 002; Huan-Neng Ron Chen; Chewnpu Jou; Jason Cong; Tatsuo Itoh; Mau-Chung Frank Chang (IEEE J. Solid State Circuits, 2019)

A New Asynchronous RTK Method to Mitigate Base Station Observation Outages. - Yuan Du; Guanwen Huang; Qin Zhang 010; Yang Gao 004; Yuting Gao (Sensors, 2019)

An Analog Neural Network Computing Engine Using CMOS-Compatible Charge-Trap-Transistor (CTT). - Yuan Du; Li Du; Xuefeng Gu; Jieqiong Du; X. Shawn Wang; Boyu Hu; Mingzhe Jiang; Xiaoliang Chen; Subramanian S. Iyer; Mau-Chung Frank Chang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019)

An 8.3% Efficiency 96-134 GHz CMOS Frequency Doubler Using Distributed Amplifier and Nonlinear Transmission Line. - Shilei Hao; Yiwu Tang; Xuan Ding; Li Du; Yuan Du; Adrian Tang 002; Qun Jane Gu; Mau-Chung Frank Chang (A-SSCC, 2020)

In-Memory Computing: The Next-Generation AI Computing Paradigm. - Yufei Ma 002; Yuan Du; Li Du; Jun Lin 001; Zhongfeng Wang 001 (ACM Great Lakes Symposium on VLSI, 2020)

A Reconfigurable Permutation Based Address Encryption Architecture for Memory Security. - Yuchen Mei; Li Du; Xuewen He; Yuan Du; Xiaoliang Chen; Zhongfeng Wang 001 (SoCC, 2020)

A 28-mW 32-Gb/s/pin 16-QAM Single-Ended Transceiver for High-Speed Memory Interface. - Jieqiong Du; Jia Zhou; Chia-Jen Liang; Boyu Hu; Yuan Du; Mau-Chung Frank Chang (VLSI Circuits, 2020)

Asynchronous RTK Method for Detecting the Stability of the Reference Station in GNSS Deformation Monitoring. - Yuan Du; Guanwen Huang; Qin Zhang 010; Yang Gao 004; Yuting Gao (Sensors, 2020)

A Reconfigurable 64-Dimension K-Means Clustering Accelerator With Adaptive Overflow Control. - Li Du; Yuan Du; Mau-Chung Frank Chang (IEEE Trans. Circuits Syst. II Express Briefs, 2020)

Flexible-width Bit-level Compressor for Convolutional Neural Network. - Junhan Zhu; Xiaoliang Chen; Li Du; Haoran Geng; Yichuan Bai; Yuandong Li; Yuan Du; Zhongfeng Wang 001 (AICAS, 2021)

A DNN Optimization Framework with Unlabeled Data for Efficient and Accurate Reconfigurable Hardware Inference. - Kai Chen; Yimin Huang; Yuan Du; Zhuang Shao; Xingyu Gu; Li Du; Zhongfeng Wang 001 (ISCAS, 2021)

LSMQ: A Layer-Wise Sensitivity-Based Mixed-Precision Quantization Method for Bit-Flexible CNN Accelerator. - Yimin Huang; Kai Chen; Zhuang Shao; Yichuan Bai; Yafeng Huang; Yuan Du; Li Du; Zhongfeng Wang 001 (ISOCC, 2021)

CTT-based Non-Volatile Deep Neural Network Accelerator Design. - Yang Xiao; Wuyu Fan; Yuan Du; Li Du; Mau-Chung Frank Chang (ISOCC, 2021)

HGFDB: a collective database of helmeted guinea fowl genomics. - Xuzhen Li; Zhi Li; Quankuan Shen; Yunbin Pan; Xiao Dong; Zetan Xu; Shengchang Duan; Yunfei Li; Yuan Du; Shanshan Chen; Zhaocheng Ma; Yang Dong (Database J. Biol. Databases Curation, 2021)

Prototype-Voxel Contrastive Learning for LiDAR Point Cloud Panoptic Segmentation. - Minzhe Liu; Qiang Zhou; Hengshuang Zhao; Jianing Li 001; Yuan Du; Kurt Keutzer; Li Du; Shanghang Zhang (ICRA, 2022)

A 3-8bit Reconfigurable Hybrid ADC Architecture with Successive-approximation and Single-slope Stages for Computing in Memory. - Wuyu Fan; Yuandong Li; Li Du; Likai Li; Yuan Du (ISCAS, 2022)

Deep Neural Network Interlayer Feature Map Compression Based on Least-Squares Fitting. - Chenjia Xie; Zhuang Shao; Hang Xu; Xiaoliang Chen; Li Du; Yuan Du; Zhongfeng Wang 001 (ISCAS, 2022)

An X-band Phase Detector Based on Quadrature Modulation in 28-nm CMOS. - Chengqiang Zhao; Wuyu Fan; Jingjing Lv; Li Du; Yuan Du (ISCAS, 2022)

SVR: A Shard-aware Vertex Reordering Method for Efficient GNN Execution and Memory Access. - Xingyuan Hu; Zhuang Shao; Chenjia Xie; Li Du; Yuan Du (ISOCC, 2022)

A Reconfigurable Design of Flexible-arbitrated Crossbar Interconnects in Multi-core SoC system. - Xuewen He; Yajie Wu; Yichuan Bai; Jie Liu; Li Du; Yuan Du (MCSoC, 2022)

EBM Life Cycle: MCMC Strategies for Synthesis, Defense, and Density Modeling. - Mitch Hill; Jonathan Mitchell; Chu Chen; Yuan Du; Mubarak Shah; Song-Chun Zhu (CoRR, 2022)

GNSS/Accelerometer Adaptive Coupled Landslide Deformation Monitoring Technology. - Ce Jing; Guanwen Huang; Qin Zhang 010; Xin Li 047; Zhengwei Bai; Yuan Du (Remote. Sens., 2022)

A Contactless Glucose Solution Concentration Measurement System Based on Improved High Accurate FMCW Radar Algorithm. - Chengjie Liu; Yuan Du; Li Du (Sensors, 2022)

A Low-Power High-Accuracy Urban Waterlogging Depth Sensor Based on Millimeter-Wave FMCW Radar. - Hanyue Shui; Haoran Geng; Qiong Li; Li Du; Yuan Du (Sensors, 2022)

Memory-Efficient CNN Accelerator Based on Interlayer Feature Map Compression. - Zhuang Shao; Xiaoliang Chen; Li Du; Lei Chen; Yuan Du; Wei Zhuang; Huadong Wei; Chenjia Xie; Zhongfeng Wang 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

An Efficient High-Throughput Structured-Light Depth Engine. - Yichuan Bai; Mingzhe Jiang; Qingyu Zhu; Xiaoliang Chen; Yuan Du; Li Du; Zhongfeng Wang 001 (IEEE Trans. Very Large Scale Integr. Syst., 2022)

Live Demonstration: An Efficient Neural Network Processor with Reduced Data Transmission and On-chip Shortcut Mapping. - Yichuan Bai; Zhuang Shao; Chenshuo Zhang; Aojie Jiang; Yuan Du; Li Du (AICAS, 2023)

A Column-Parallel Time-Interleaved SAR/SS ADC for Computing in Memory with 2-8bit Reconfigurable Resolution. - Yuandong Li; Li Du; Yuan Du (AICAS, 2023)

Grand Challenge on Software and Hardware Co-Optimization for E-Commerce Recommendation System. - Jianing Li; Jiabin Liu; Xingyuan Hu; Yuhang Zhang 008; Guosheng Yu; Shimeng Qian; Wei Mao 002; Li Du; Yongfu Li 002; Yuan Du (AICAS, 2023)

An Efficient Design Framework for 2×2 CNN Accelerator Chiplet Cluster with SerDes Interconnects. - Yajie Wu; Tianze Li; Zhuang Shao; Li Du; Yuan Du (AICAS, 2023)

A Dual-Mode Broadband Image Sensor Based on Graphene-CMOS Integration. - Ye Lin; Yang Xiao; Jingjing Lv; Li Du; Yuan Du (ASICON, 2023)

A Non-Centralized Routing Scheme with Phase-Caching CDR for Nanosecond-Level Optical Switching Systems. - Xin Lu; Heng Zhang 013; Leilei Wang; Tao Fang; Chunhui Zhang; Feng Wang; Li Du; Yashe Liu; Xiangfei Chen; Yuan Du (ASICON, 2023)

Memory-Efficient Compression Based on Least-Squares Fitting in Convolutional Neural Network Accelerators. - Hang Xu; Chenjia Xie; Xin Lu; Li Du; Yuan Du (ASICON, 2023)

Linearity Analysis for Charge Domain In-memory Computing. - Heng Zhang; Yuan Du; Li Du (ASICON, 2023)

QD-BEV : Quantization-aware View-guided Distillation for Multi-view 3D Object Detection. - Yifan Zhang; Zhen Dong 003; Huanrui Yang; Ming Lu; Cheng-Ching Tseng; Yuan Du; Kurt Keutzer; Li Du; Shanghang Zhang (ICCV, 2023)

Siamese Network Representation for Active Learning. - Jianing Li; Yuan Du; Li Du (ICIP, 2023)

Graph Neural Network Assisted S-Parameter Inference and Control-Word Generation of Terahertz Reconfigurable Intelligent Surface. - Zihan Ning; Tong Sun; Jizhao Li; Yanfei Ren; Chenjia Xie; Li Du; Lianggong Wen; Yuan Du (ICTA, 2023)

Characterization of Charge-Trap-Transistor (CTT) Threshold Voltage Degradation and Differential-Pair-Based Memory Design. - Zhichao Chen; Yang Xiao; Li Du; Yuan Du (ISCAS, 2023)

Unimodal Training-Multimodal Prediction: Cross-modal Federated Learning with Hierarchical Aggregation. - Rongyu Zhang; Xiaowei Chi; Guiliang Liu; Wenyi Zhang; Yuan Du; Fangxin Wang 001 (CoRR, 2023)

Efficient Deweather Mixture-of-Experts with Uncertainty-aware Feature-wise Linear Modulation. - Rongyu Zhang; Yulin Luo; Jiaming Liu 003; Huanrui Yang; Zhen Dong 003; Denis A. Gudovskiy; Tomoyuki Okuno; Yohei Nakata; Kurt Keutzer; Yuan Du; Shanghang Zhang (CoRR, 2023)

A 0.90-Tb/s/in 1.29-pJ/b Wireline Transceiver With Single-Ended Crosstalk Cancellation Coding Scheme for High-Density Interconnects. - Qian Liu; Li Du; Yuan Du (IEEE J. Solid State Circuits, 2023)

Progressive Classifier Mechanism for Bridge Expansion Joint Health Status Monitoring System Based on Acoustic Sensors. - Xulong Zhang 007; Zihao Cheng; Li Du; Yuan Du (Sensors, 2023)

QPA: A Quantization-Aware Piecewise Polynomial Approximation Methodology for Hardware-Efficient Implementations. - Haoran Geng; Xiaoliang Chen; Ning Zhao; Yuan Du; Li Du (IEEE Trans. Very Large Scale Integr. Syst., 2023)

An Efficient CNN Inference Accelerator Based on Intra- and Inter-Channel Feature Map Compression. - Chenjia Xie; Zhuang Shao; Ning Zhao; Yuan Du; Li Du (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

Design of All-Digital Two Phase Ping-Pong Switched Capacitor Voltage Doubler Power Converter. - Zhiwen Gu; Feng Yang; Yuhang Zhang 008; Yanhan Zeng; Zhihong Luo; Yuan Du; Li Du; Yongfu Li 002 (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

SSM-CIM: An Efficient CIM Macro Featuring Single-Step Multi-bit MAC Computation for CNN Edge Inference. - Heng Zhang; Sunan He; Xin Lu; Xinjie Guo; Shaodi Wang; Yuan Du; Li Du (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

Efficient Deweahter Mixture-of-Experts with Uncertainty-Aware Feature-Wise Linear Modulation. - Rongyu Zhang; Yulin Luo; Jiaming Liu 003; Huanrui Yang; Zhen Dong 003; Denis A. Gudovskiy; Tomoyuki Okuno; Yohei Nakata; Kurt Keutzer; Yuan Du; Shanghang Zhang (AAAI, 2024)

An Area-Efficient CNN Accelerator Supporting Global Average Pooling with Arbitrary Shapes. - Yichuan Bai; Xiaopeng Zhang; Qian Wang; Jingjing Lv; Lei Chen; Yuan Du; Li Du (AICAS, 2024)

A CNN-based One-shot Blind RX-side-only Equalization Scheme for High-speed SerDes links. - Yiheng Hui; Yuanlin Nong; He Ma; Jingjing Lv; Lei Chen; Li Du; Yuan Du (AICAS, 2024)

AICAS Grand Challenge 2024: Software and Hardware Co-optimization for General Large Language Model Inference on CPU. - Junfeng Tan; Guosheng Yu; Jianing Li; Xiaohan Ma; Fang Bao; Evens Pan; David Bian; Yongfu Li 002; Yuan Du; Li Du; Bo Li; Wei Mao 002 (AICAS, 2024)

A 500MHz, 0.5% THD With 400mVpp Linear Transimpedance Amplifier (TIA) for Analog Optical and In-memory Computing Applications. - Kuanyu Gu; Zhan Ning; Likai Li; Jingjing Lv; Zhong Zhang; Li Du; Yuan Du (APCCAS, 2024)

An Efficient On-Chip Storage Solution for CNN Accelerator Based on Self-tuning and Co-scheduling. - Chengrui Li; Ning Zhao; Xiaopeng Zhang; Wei Gao; Chenjia Xie; Yuan Du; Li Du (APCCAS, 2024)

A Resource-Efficient Weight Quantization and Mapping Method for Crossbar Arrays in ReRAM-based Computing-in-Memory Systems. - Mingyuan Ma; Wei Jiang; Juntao Liu; Li Du; Zhongyuan Ma; Yuan Du (APCCAS, 2024)

A Streaming Transformer Accelerator with Efficient On-Chip Normalization. - Ning Zhao; Jiayuan Chen; Jingjing Lv; Chenjia Xie; Yuan Du; Li Du (APCCAS, 2024)

Artificial Intelligence Design for Real-time Fall Detection. - Zixuan Wang; Yuqi Wu; Shuren Wang; Xihua Wang; Li Du; Yuan Du; Jie Chen (BioCAS, 2024)

SFC: Achieve Accurate Fast Convolution under Low-precision Arithmetic. - Liulu He; Yufei Zhao; Rui Gao; Yuan Du; Li Du (ICML, 2024)

Optoelectronic Computing Evaluation and Deployment Platform Based on a 256-MAC Silicon Photonic Chip. - Likai Li; Yichuan Bai; Shengping Liu; Yang Zhao; Sunan He; Yaqing Li; Li Du; Yuan Du (ISCAS, 2024)

VeCAF: Vision-language Collaborative Active Finetuning with Training Objective Awareness. - Rongyu Zhang; Zefan Cai; Huanrui Yang; Zidong Liu; Denis A. Gudovskiy; Tomoyuki Okuno; Yohei Nakata; Kurt Keutzer; Baobao Chang; Yuan Du; Li Du; Shanghang Zhang (ACM Multimedia, 2024)

VeCAF: VLM-empowered Collaborative Active Finetuning with Training Objective Awareness. - Rongyu Zhang; Zefan Cai; Huanrui Yang; Zidong Liu; Denis A. Gudovskiy; Tomoyuki Okuno; Yohei Nakata; Kurt Keutzer; Baobao Chang; Yuan Du; Li Du; Shanghang Zhang (CoRR, 2024)

Intuition-aware Mixture-of-Rank-1-Experts for Parameter Efficient Finetuning. - Yijiang Liu; Rongyu Zhang; Huanrui Yang; Kurt Keutzer; Yuan Du; Li Du; Shanghang Zhang (CoRR, 2024)

Decomposing the Neurons: Activation Sparsity via Mixture of Experts for Continual Test Time Adaptation. - Rongyu Zhang; Aosong Cheng; Yulin Luo; Gaole Dai; Huanrui Yang; Jiaming Liu 003; Ran Xu 013; Li Du; Yuan Du; Yanbing Jiang; Shanghang Zhang (CoRR, 2024)

Fisher-aware Quantization for DETR Detectors with Critical-category Objectives. - Huanrui Yang; Yafeng Huang; Zhen Dong 003; Denis A. Gudovskiy; Tomoyuki Okuno; Yohei Nakata; Yuan Du; Kurt Keutzer; Shanghang Zhang (CoRR, 2024)

AmpAgent: An LLM-based Multi-Agent System for Multi-stage Amplifier Schematic Design from Literature for Process and Performance Porting. - Chengjie Liu; Weiyu Chen; Anlan Peng; Yuan Du; Li Du; Jun Yang (CoRR, 2024)

Special Issue on Selected Papers From APCCAS 2022. - Yan Liu 016; Yuan Du; Yang Zhao 007 (IEEE Open J. Circuits Syst., 2024)

BEV-LGKD: A Unified LiDAR-Guided Knowledge Distillation Framework for Multi-View BEV 3D Object Detection. - Jianing Li 001; Ming Lu; Jiaming Liu 003; Yandong Guo; Yuan Du; Li Du; Shanghang Zhang (IEEE Trans. Intell. Veh., 2024)

An Efficient GCN Accelerator Based on Workload Reorganization and Feature Reduction. - Zhuang Shao; Chenjia Xie; Zihan Ning; Qi Wu; Liang Chang 002; Yuan Du; Li Du (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

Low-Latency PAE: Permutation-Based Address Encryption Hardware Engine for IoT Real-Time Memory Protection. - Xuewen He; Yichuan Bai; Yujia Liu; Li Du; Zhongfeng Wang 001; Yuan Du (IEEE Internet Things J., 2024)

An Energy-Efficient Spiking Neural Network Accelerator Based on Spatio-Temporal Redundancy Reduction. - Chenjia Xie; Zhuang Shao; Zhichao Chen; Yuan Du; Li Du (IEEE Trans. Very Large Scale Integr. Syst., 2024)

GroupQ: Group-Wise Quantization With Multi-Objective Optimization for CNN Accelerators. - Aojie Jiang; Li Du; Yuan Du (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

A Compilation Framework for SRAM Computing-in-Memory Systems With Optimized Weight Mapping and Error Correction. - Yichuan Bai; Yaqing Li; Heng Zhang; Aojie Jiang; Yuan Du; Li Du (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

Privacy-Preserving Combined Heat and Power Dispatch Based on Information Masking Mechanism: A Decentralized Perspective. - Leilei Zhao; Yixun Xue; Yuan Du; Xinyue Chang; Zening Li; Jia Su; Hongbin Sun 002 (IEEE Trans. Smart Grid, 2024)

An Efficient Two-Stage Pipelined Compute-in-Memory Macro for Accelerating Transformer Feed-Forward Networks. - Heng Zhang; Wenhe Yin; Sunan He; Yuan Du; Li Du (IEEE Trans. Very Large Scale Integr. Syst., 2024)

Chaotic Video Encryption Based on DNA Coding, Confusion, and Diffusion. - Li-Xun Zhi; Yuan Du; Xi-Jue Zhao; Tao Chen; Ke-Yin Cao; Dong Jiang (Int. J. Bifurc. Chaos, 2024)

An 11T1C Bit-Level-Sparsity-Aware Computing- in-Memory Macro With Adaptive Conversion Time and Computation Voltage. - Ye Lin; Yuandong Li; Heng Zhang; He Ma; Jingjing Lv; Anying Jiang; Yuan Du; Li Du (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

An Offset-Cancellation Technique Using Charge-Trap Transistors and Asynchronous Programming Scheme. - Ye Lin; Anying Jiang; Jingjing Lv; Yuan Du; Li Du (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

Elimination of Non-Idealities for Multi-Channel Phased Array Systems with Zero-IF Receiver. - Yiping Shi; Mingyuan Ma; Sunan He; Yanfei Ren; Li Du; Yuan Du (J. Signal Process. Syst., 2024)

PAT: Pruning-Aware Tuning for Large Language Models. - Yijiang Liu; Huanrui Yang; Youxin Chen; Rongyu Zhang; Miao Wang; Yuan Du; Li Du (AAAI, 2025)

A 65nm 100MS/s-400MS/s Multi-Column SAR/SS ADC with Reconfigurable 2-8 Bit Resolution for Optical and In-memory Computing. - Anying Jiang; Ye Lin; Jiayuan Chen; Wenhe Yin; Yize Wang; Mingqian Yang; Li Du; Yuan Du (ISCAS, 2025)

FBQuant: FeedBack Quantization for Large Language Models. - Yijiang Liu; Hengyu Fang; Liulu He; Rongyu Zhang; Yichuan Bai; Yuan Du; Li Du (CoRR, 2025)

A Fast-Convergence Near-Memory-Computing Accelerator for Solving Partial Differential Equations. - Chenjia Xie; Zhuang Shao; Ning Zhao; Xingyuan Hu; Yuan Du; Li Du (IEEE Trans. Very Large Scale Integr. Syst., 2025)

MoLe-VLA: Dynamic Layer-skipping Vision Language Action Model via Mixture-of-Layers for Efficient Robot Manipulation. - Rongyu Zhang; Menghang Dong; Yuan Zhang 020; Liang Heng; Xiaowei Chi; Gaole Dai; Li Du; Dan Wang 002; Yuan Du; Shanghang Zhang (CoRR, 2025)

Low-Latency DAE: A Configurable Lightweight Hybrid Data and Address Encryption Engine for IoT Real-Time NVM Protection. - Xuewen He; Li Du; Yuan Du (IEEE Internet Things J., 2025)

BEVUDA++: Geometric-Aware Unsupervised Domain Adaptation for Multi-View 3D Object Detection. - Rongyu Zhang; Jiaming Liu 003; Xiaoqi Li 009; Xiaowei Chi; Dan Wang 002; Li Du; Yuan Du; Shanghang Zhang (IEEE Trans. Circuits Syst. Video Technol., 2025)

BASE-Q: Bias and Asymmetric Scaling Enhanced Rotational Quantization for Large Language Models. - Liulu He; Shenli Zhen; Karwei Sun; Yijiang Liu; Yufei Zhao; Chongkang Tan; Huanrui Yang; Yuan Du; Li Du (CoRR, 2025)

A Large Language Model-based Multi-Agent Framework for Analog Circuits' Sizing Relationships Extraction. - Chengjie Liu; Weiyu Chen; Huiyao Xu; Yuan Du; Jun Yang; Li Du (CoRR, 2025)

DiffCkt: A Diffusion Model-Based Hybrid Neural Network Framework for Automatic Transistor-Level Generation of Analog Circuits. - Chengjie Liu; Jiajia Li; Yabing Feng; Wenhao Huang; Weiyu Chen; Yuan Du; Jun Yang; Li Du (CoRR, 2025)

AnalogTester: A Large Language Model-Based Framework for Automatic Testbench Generation in Analog Circuit Design. - Weiyu Chen; Chengjie Liu; Wenhao Huang; Jinyang Lyu; Mingqian Yang; Yuan Du; Li Du; Jun Yang (CoRR, 2025)

BE-NPU: A Bandwidth-Efficient Neural Processing Unit With Adaptive Processing Schemes for Reduced Off-Chip Bandwidth Demand. - Yichuan Bai; Xiaopeng Zhang; Qian Wang; Yaqing Li; Yuan Du; Li Du (IEEE Trans. Computers, 2025)

RepCaM++: Exploring Transparent Visual Prompt With Inference-Time Re-Parameterization for Neural Video Delivery. - Rongyu Zhang; Xize Duan; Jiaming Liu 003; Li Du; Yuan Du; Dan Wang 002; Shanghang Zhang; Fangxin Wang 001 (IEEE Trans. Mob. Comput., 2025)