Low-Complexity Bit-Parallel Systolic Multipliers over GF(2m). - Chiou-Yng Lee; Chin-Chin Chen; Yuan-Ho Chen; Erl-Huei Lu (SMC, 2006)

Robust$H_infty$Power Control for CDMA Cellular Communication Systems. - Bore-Kuen Lee; Yuan-Ho Chen; Bor-Sen Chen (IEEE Trans. Signal Process., 2006)

Power control for CDMA cellular radio systems via l1 optimal predictor. - Bor-Sen Chen; Bore-Kuen Lee; Yuan-Ho Chen (IEEE Trans. Wirel. Commun., 2006)

Area-Effective and Power-Efficient Fixed-Width Booth Multipliers Using Generalized Probabilistic Estimation Bias. - Yuan-Ho Chen; Chung-Yi Li; Tsin-Yuan Chang (IEEE J. Emerg. Sel. Topics Circuits Syst., 2011)

A Probabilistic Estimation Bias Circuit for Fixed-Width Booth Multiplier and Its DCT Applications. - Chung-Yi Li; Yuan-Ho Chen; Tsin-Yuan Chang; Jyun-Neng Chen (IEEE Trans. Circuits Syst. II Express Briefs, 2011)

High Throughput DA-Based DCT With High Accuracy Error-Compensated Adder Tree. - Yuan-Ho Chen; Tsin-Yuan Chang; Chung-Yi Li (IEEE Trans. Very Large Scale Integr. Syst., 2011)

Integrated model of hot spring service quality perceptions under uncertainty. - Ming-Lang Tseng; Yuan-Ho Chen; Yong Geng (Appl. Soft Comput., 2012)

A High-Accuracy Adaptive Conditional-Probability Estimator for Fixed-Width Booth Multipliers. - Yuan-Ho Chen; Tsin-Yuan Chang (IEEE Trans. Circuits Syst. I Regul. Pap., 2012)

A High Performance Video Transform Engine by Using Space-Time Scheduling Strategy. - Yuan-Ho Chen; Tsin-Yuan Chang (IEEE Trans. Very Large Scale Integr. Syst., 2012)

Period Extension and Randomness Enhancement Using High-Throughput Reseeding-Mixing PRNG. - Chung-Yi Li; Yuan-Ho Chen; Tsin-Yuan Chang; Lih-Yuan Deng; Kiwing To (IEEE Trans. Very Large Scale Integr. Syst., 2012)

A high resolution FPGA-based merged delay line TDC with nonlinearity calibration. - Yuan-Ho Chen (ISCAS, 2013)

E-leadership effectiveness in virtual teams: motivating language perspective. - Kai-Tang Fan; Yuan-Ho Chen; Ching-Wen Wang; Minder Chen (Ind. Manag. Data Syst., 2014)

Hardware-Efficient Multi-Standard Video Transform Core. - Yuan-Ho Chen; Hsiao-Tzu Liu (J. Circuits Syst. Comput., 2014)

A Multi-stage Fault-Tolerant Multiplier with Triple Module Redundancy (TMR) Technique. - Yuan-Ho Chen; Chih-Wen Lu; Shian-Shing Shyu; Chung-Lin Lee; Ting-Chia Ou (J. Circuits Syst. Comput., 2014)

High-Throughput Multistandard Transform Core Supporting MPEG/H.264/VC-1 Using Common Sharing Distributed Arithmetic. - Yuan-Ho Chen; Jyun-Neng Chen; Tsin-Yuan Chang; Chih-Wen Lu (IEEE Trans. Very Large Scale Integr. Syst., 2014)

A High-Throughput and Area-Efficient Video Transform Core With a Time Division Strategy. - Yuan-Ho Chen; Ruei-Yuan Jou; Tsin-Yuan Chang; Chih-Wen Lu (IEEE Trans. Very Large Scale Integr. Syst., 2014)

Hardware Design and Implementation of a Wavelet De-Noising Procedure for Medical Signal Preprocessing. - Szi-Wen Chen; Yuan-Ho Chen (Sensors, 2015)

Area-Efficient Fixed-Width Squarer With Dynamic Error-Compensation Circuit. - Yuan-Ho Chen (IEEE Trans. Circuits Syst. II Express Briefs, 2015)

High-Accuracy Fixed-Width Booth Multipliers Based on Probability and Simulation. - Wen-Quan He; Yuan-Ho Chen; Shyh-Jye Jou (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

An Accuracy-Adjustment Fixed-Width Booth Multiplier Based on Multilevel Conditional Probability. - Yuan-Ho Chen (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Dynamic Error-Compensated Fixed-Width Booth Multiplier Based on Conditional-Probability of Input Series. - Wen-Quan He; Yuan-Ho Chen; Shyh-Jye Jou (Circuits Syst. Signal Process., 2016)

Low-cost multi-standard simultaneous forward and inverse video transform core. - Yun-Hua Tseng; Yuan-Ho Chen; Tze-Yang Kao; Chih-Wen Lu (Int. J. Circuit Theory Appl., 2016)

High-throughput IDCT architecture for high-efficiency video coding (HEVC). - Yuan-Ho Chen; Yi-Fan Ko (Int. J. Circuit Theory Appl., 2017)

Adaptive Integration of the Compressed Algorithm of CS and NPC for the ECG Signal Compressed Algorithm in VLSI Implementation. - Yun-Hua Tseng; Yuan-Ho Chen; Chih-Wen Lu (Sensors, 2017)

Multiple Leads With a Switch Mode for Lossless and Lossy Compression Using Very-Large-Scale Integration Technology. - Yun-Hua Tseng; Yuan-Ho Chen; Chih-Wen Lu (IEEE Access, 2018)

Fine-Tuning Accuracy Using Conditional Probability of the Bottom Sign-Bit in Fixed-Width Modified Booth Multiplier. - Yuan-Ho Chen; Chung-Yi Li; Luhua Lai (Circuits Syst. Signal Process., 2018)

Cost-effective multi-standard video transform core using time-sharing architecture. - Yun-Hua Tseng; Yuan-Ho Chen (EURASIP J. Adv. Signal Process., 2019)

Run-time calibration scheme for the implementation of a robust field-programmable gate array-based time-to-digital converter. - Yuan-Ho Chen (Int. J. Circuit Theory Appl., 2019)

Premature Ventricular Complex Detection Chip Obtained Using Convolution Neural Network. - Yu-Lun Huang; Pei-Jung Chang; Yuan-Ho Chen (ICAIIC, 2020)

VLSI Implementation of a Cost-Efficient 3-Lead Lossless ECG Compressor and Decompressor. - Yuan-Ho Chen; Yun-Hua Tseng; Pao-Hsien Chu; Yen Juan; Shun-Ping Wang (Circuits Syst. Signal Process., 2020)

A low-area high-efficiency video coding inverse transform core using resource and time sharing architecture. - Yuan-Ho Chen; Chieh-Yang Liu (EURASIP J. Adv. Signal Process., 2020)

A VLSI Implementation of Independent Component Analysis for Biomedical Signal Separation Using CORDIC Engine. - Yuan-Ho Chen; Szi-Wen Chen; Min-Xian Wei (IEEE Trans. Biomed. Circuits Syst., 2020)

Low-Cost Implementation of Independent Component Analysis for Biomedical Signal Separation Using Very-Large-Scale Integration. - Yuan-Ho Chen; Shun-Ping Wang (IEEE Trans. Circuits Syst., 2020)

Simple and hardware-efficient row-based direct-mapping estimators in fixed-width modified Booth multipliers. - Chung-Yi Li; Yuan-Ho Chen; Lu-An Lai; Wen-Chi Ye; Jun Yang (Int. J. Circuit Theory Appl., 2021)

Improvement of Accuracy of Fixed-Width Booth Multipliers Using Data Scaling Technology. - Yuan-Ho Chen (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

High Accuracy Abnormal ECG Detection Chip Using a Simple Neural Network. - Kai-Fen Chang; Yuan-Ho Chen (ISOCC, 2022)

Very-large-scale Integration of a Dual-lead Electrocardiogram Compression Chip with Modified Huffman Encoding. - Yi-Fan Chen; Wei-Jhong Huang; Yi-Wei Zeng; Hsin-Tung Hua; Kai-Fen Chang; Yuan-Ho Chen (LifeTech, 2022)

VLSI Implementation of QRS Complex Detector Based on Wavelet Decomposition. - Yuan-Ho Chen; Chih-Wen Lu; Szi-Wen Chen; Ming-Han Tsai; Shinn-Yn Lin; Rou-Shayn Chen (IEEE Access, 2022)

Very Large-Scale Integration for Premature Ventricular Contraction Detection Using a Convolutional Neural Network. - Yuan-Ho Chen; Hsin-Tung Hua (J. Circuits Syst. Comput., 2022)

A VLSI Chip for the Abnormal Heart Beat Detection Using Convolutional Neural Network. - Yuan-Ho Chen; Szi-Wen Chen; Pei-Jung Chang; Hsin-Tung Hua; Shinn-Yn Lin; Rou-Shayn Chen (Sensors, 2022)

Hybrid CNN-LSTM Network for ECG Classification and Its Software-Hardware Co-Design Approach. - Song-Nien Tang; Yuan-Ho Chen; Yu-Wei Chang; Yu-Ting Chen; Shuo-Hung Chou (ISOCC, 2023)

An Automated Toolchain for QUBO-based Optimization with Quantum-inspired Annealers. - Yun-Ting Zhang; Chin-Fu Nien; Chia-Wei Lin; Wen-Jui Chao; Chen-Yu Liu; Lien-Po Yu; Yuan-Ho Chen (ISOCC, 2023)

Simulated Annealing Hardware Architecture for Max-Cut Combinatorial Optimization. - Szu-Wei Chien; Yuan-Ho Chen (GCCE, 2024)

A Simplified Simulated Annealing Algorithm and Its Implementation. - Wu-Hsun Chu; Yuan-Ho Chen (GCCE, 2024)

VLSI Implementation of Recursive CNNs with Multi-Scale Integration for Image Classification Improvement. - Kai-Fen Chang; Yuan-Ho Chen (TENCON, 2024)

A Very Large-Scale Integration (VLSI) Chip Design for Abnormal Heartbeat Detection Using a Data-Shifting Neural Network (DSNN). - Yuan-Ho Chen; Szi-Wen Chen; Hong-Wen Jian; Shinn-Yn Lin; Rou-Shayn Chen (IEEE Access, 2024)

Design and Implementation of a VLSI-based Annealing Accelerator for Efficiently Solving Combinatorial Optimization Problems. - Yuan-Ho Chen; Che-An Chou; Chin-Fu Nien; Shinn-Yn Lin (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

Corrections to "A Very Large-Scale Integration (VLSI) Chip Design for Abnormal Heartbeat Detection Using a Data-Shifting Neural Network (DSNN)". - Yuan-Ho Chen; Szi-Wen Chen; Hong-Wen Jian; Shinn-Yn Lin; Rou-Shayn Chen (IEEE Access, 2025)

Low-latency and power-efficient row-based binary-weighted compensator for fixed-width Booth multiplier. - Chung-Yi Li; Hong-Chi Hu; Yuan-Ho Chen; Shinn-Yn Lin (Int. J. Circuit Theory Appl., 2025)