A high throughput VLSI design with hybrid memory architecture for H.264/AVC CABAC decoder. - Yuan-Hsin Liao; Gwo-Long Li; Tian-Sheuan Chang (ISCAS, 2010)

A 135 MHz 542 k Gates High Throughput H.264/AVC Scalable High Profile Decoder. - Gwo-Long Li; Yu-Chen Chen; Yuan-Hsin Liao; Po-Yuan Hsu; Meng-Hsun Wen; Tian-Sheuan Chang (IEEE Trans. Circuits Syst. Video Technol., 2012)

A Highly Efficient VLSI Architecture for H.264/AVC Level 5.1 CABAC Decoder. - Yuan-Hsin Liao; Gwo-Long Li; Tian-Sheuan Chang (IEEE Trans. Circuits Syst. Video Technol., 2012)

A 385 MHz 13.54 K Gates Delay Balanced Two-Level CAVLC Decoder for Ultra HD H.264/AVC Video. - Yuan-Hsin Liao; Gwo-Long Li; Tian-Sheuan Chang (IEEE Trans. Circuits Syst. Video Technol., 2012)

Object-based on-line video summarization for internet of video things. - Shih-Ting Lin; Yuan-Hsin Liao; Yu Tsao 001; Shao-Yi Chien (ISCAS, 2017)