Low-Voltage Low-Power CMOS True-Single-Phase Clocking Scheme with Locally Asynchronous Logic Circuits. - Hong-Yi Huang; Jinn-Shyan Wang; Yuan-Hua Chu; Tain-Shun Wu; Kuo-Hsing Cheng; Chung-Yu Wu (ISCAS, 1995)

The new approach of programmable pseudo fractional-N clock generator for GHz operation with 50% duty cycle. - Wei-Bin Yang; Shu-Chang Kuo; Yuan-Hua Chu; Kuo-Hsing Cheng (ECCTD, 2005)

Design of STR level converters for SoCs using the multi-island dual-VDD design technique. - Jinn-Shyan Wang; Yu-Juey Chang; Chingwei Yeh; Yuan-Hua Chu (ISCAS, 2006)

Full System Simulation and Verification Framework. - Jing-Wun Lin; Chen-Chieh Wang; Chin-Yao Chang; Chung-Ho Chen; Kuen-Jong Lee; Yuan-Hua Chu; Jen-Chieh Yeh; Ying-Chuan Hsiao (IAS, 2009)

Collaborative voltage scaling with online STA and variable-latency datapath. - Tay-Jyi Lin; Pi-Chen Hsiao; Chi-Hung Lin; Shu-Chang Kuo; Chou-Kun Lin; Yu-Ting Kuo; Chih-Wei Liu; Yuan-Hua Chu (ACM Great Lakes Symposium on VLSI, 2010)

A 0.29V embedded NAND-ROM in 90nm CMOS for ultra-low-voltage applications. - Meng-Fan Chang; Shu-Meng Yang; Chih-Wei Liang; Chih-Chyuang Chiang; Pi-Feng Chiu; Ku-Feng Lin; Yuan-Hua Chu; Wen-Chin Wu; Hiroyuki Yamauchi (ISSCC, 2010)

Energy-efficient real-time scheduling of multimedia tasks on multi-core processors. - Yi-Hung Wei; Chuan-Yue Yang; Tei-Wei Kuo; Shih-Hao Hung; Yuan-Hua Chu (SAC, 2010)

0.5 VDD digitally controlled oscillators design with compensation techniques for PVT variations. - Chia-Wen Chang; Shyh-Jye Jou; Yuan-Hua Chu (ASICON, 2011)

A Large Sigma V TH /VDD Tolerant Zigzag 8T SRAM With Area-Efficient Decoupled Differential Sensing and Fast Write-Back Scheme. - Jui-Jen Wu; Yen-Hui Chen; Meng-Fan Chang; Po-Wei Chou; Chien-Yuan Chen; Hung-Jen Liao; Ming-Bin Chen; Yuan-Hua Chu; Wen-Chin Wu; Hiroyuki Yamauchi (IEEE J. Solid State Circuits, 2011)

Parallel Architecture Core (PAC) - the First Multicore Application Processor SoC in Taiwan Part I: Hardware Architecture & Software Development Tools. - David Chih-Wei Chang; Tay-Jyi Lin; Chung-Ju Wu; Jenq Kuen Lee; Yuan-Hua Chu; An-Yeu Wu (J. Signal Process. Syst., 2011)

Energy-efficient RISC design with on-demand circuit-level timing speculation. - Tay-Jyi Lin; Yu-Ting Kuo; Yu-Jung Tsai; Ting-Yu Shyu; Yuan-Hua Chu (ASP-DAC, 2012)

Thermoelectric energy harvesting with 1mV low input voltage and 390nA quiescent current for 99.6% maximum power point tracking. - Chao-Jen Huang; Wei-Chung Chen; Chia-Lung Ni; Ke-Horng Chen; Chien-Chun Lu; Yuan-Hua Chu; Ming-Ching Kuo (ESSCIRC, 2012)

An ultra-low power interface CMOS IC design for biosensor applications. - Weibo Hu; Yen-Ting Liu; Vighnesh Das; Cliff Schecht; Tam Q. Nguyen; Donald Y. C. Lie; Tzu-Chao Yan; Chien-Nan Kuo; Stanley Wu; Yuan-Hua Chu; Tzu-Yi Yang (MWSCAS, 2012)

An energy-efficient level converter with high thermal variation immunity for sub-threshold to super-threshold operation. - Mei-Wei Chen; Ming-Hung Chang; Yuan-Hua Chu; Wei Hwang (SoCC, 2012)

A 260mV L-shaped 7T SRAM with bit-line (BL) Swing expansion schemes based on boosted BL, asymmetric-VTH read-port, and offset cell VDD biasing techniques. - Ming-Pin Chen; Lai-Fu Chen; Meng-Fan Chang; Shu-Meng Yang; Yao-Jen Kuo; Jui-Jen Wu; Mon-Shu Ho; Hsiu-Yun Su; Yuan-Hua Chu; Wen-Chin Wu; Tzu-Yi Yang; Hiroyuki Yamauchi (VLSIC, 2012)

A 0.48V 0.57nJ/pixel video-recording SoC in 65nm CMOS. - Tay-Jyi Lin; Cheng-An Chien; Pei-Yao Chang; Ching-Wen Chen; Po-Hao Wang; Ting-Yu Shyu; Chien-Yung Chou; Shien-Chun Luo; Jiun-In Guo; Tien-Fu Chen; Gene C. H. Chuang; Yuan-Hua Chu; et al. (ISSCC, 2013)

A dual-edged triggered explicit-pulsed level converting flip-flop with a wide operation range. - Mei-Wei Chen; Ming-Hung Chang; Pei-Chen Wu; Yi-Ping Kuo; Chun-Lin Yang; Yuan-Hua Chu; Wei Hwang (SoCC, 2013)

A Sub-0.3 V Area-Efficient L-Shaped 7T SRAM With Read Bitline Swing Expansion Schemes Based on Boosted Read-Bitline, Asymmetric-VTH Read-Port, and Offset Cell VDD Biasing Techniques. - Meng-Fan Chang; Ming-Bin Chen; Lai-Fu Chen; Shu-Meng Yang; Yao-Jen Kuo; Jui-Jen Wu; Hsiu-Yun Su; Yuan-Hua Chu; Wen-Chin Wu; Tzu-Yi Yang; Hiroyuki Yamauchi (IEEE J. Solid State Circuits, 2013)

An Adaptive Pulse-Triggered Flip-Flop for a High-Speed and Voltage-Scalable Standard Cell Library. - Shien-Chun Luo; Ching-Ji Huang; Yuan-Hua Chu (IEEE Trans. Circuits Syst. II Express Briefs, 2013)

A 3 MHz-to-1.8 GHz 94 μW-to-9.5 mW 0.0153-mm2 all-digital delay-locked loop in 65-nm CMOS. - Chun-Yuan Cheng; Jinn-Shyan Wang; Pei-Yuan Chou; Shiou-Ching Chen; Chi-Tien Sun; Yuan-Hua Chu; Tzu-Yi Yang (A-SSCC, 2014)

Low power fixed-latency DSP accelerator with autonomous minimum energy tracking (AMET). - Chung-Hsun Huang; Wei-Jen Chen; Keng-Jui Chang; Yi-Hsuan Ting; Keng-Chang Hsu; Yu-Fu Pan; Chao-Chun Chen; Yuan-Hua Chu; Tay-Jyi Lin; Jinn-Shyan Wang (Hot Chips Symposium, 2014)

An ultra-low voltage hearing aid chip using variable-latency design technique. - Kuo-Chiang Chang; Shien-Chun Luo; Ching-Ji Huang; Chih-Wei Liu; Yuan-Hua Chu; Shyh-Jye Jou (ISCAS, 2014)

A radio-controlled receiver for clocks/watches and alarm applications. - Jen-Chieh Liu; Huan-Ke Chiu; Jia-Hung Peng; Yuan-Hua Chu; Hong-Yi Huang (ISCAS, 2014)

PVT-aware digital controlled voltage regulator design for ultra-low-power (ULP) DVFS systems. - Pei-Chen Wu; Yi-Ping Kuo; Chung-Shiang Wu; Ching-Te Chuang; Yuan-Hua Chu; Wei Hwang (SoCC, 2014)

40 nm Bit-Interleaving 12T Subthreshold SRAM With Data-Aware Write-Assist. - Yi-Wei Chiu; Yu-Hao Hu; Ming-Hsien Tu; Jun-Kai Zhao; Yuan-Hua Chu; Shyh-Jye Jou; Ching-Te Chuang (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)

Separate Clock Network Voltage for Correcting Random Errors in ULV Clocked Storage Cells. - Shien-Chun Luo; Kuo-Chiang Chang; Ming-Pin Chen; Ching-Ji Huang; Yi-Fang Chiu; Po-Hsun Chen; Liang-Chia Cheng; Chih-Wei Liu; Yuan-Hua Chu (IEEE Trans. Circuits Syst. II Express Briefs, 2014)

A Wide-Range Level Shifter Using a Modified Wilson Current Mirror Hybrid Buffer. - Shien-Chun Luo; Ching-Ji Huang; Yuan-Hua Chu (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)

An all-digital power management unit with 90% power efficiency and ns-order voltage transition time for DVS operation in low power sensing SoC applications. - Chung-Shiang Wu; Kai-Chun Lin; Yi-Ping Kuo; Po-Hung Chen; Yuan-Hua Chu; Wei Hwang (ISCAS, 2015)

All digitally controlled linear voltage regulator with PMOS strength self-calibration for ripple reduction. - Yi-Ping Kuo; Po-Tsang Huang; Chung-Shiang Wu; Yu-Jie Liang; Ching-Te Chuang; Yuan-Hua Chu; Wei Hwang (VLSI-DAT, 2015)

A Near-Threshold Cell-Based All-Digital PLL with Hierarchical Band-Selection G-DCO for Fast Lock-In and Low-Power Applications. - Chia-Wen Chang; Yuan-Hua Chu; Shyh-Jye Jou (IEICE Trans. Electron., 2015)

Invited - Wireless sensor nodes for environmental monitoring in internet of things. - Ting-Chou Lu; Li-Ren Huang; Yu Lee; Kun-Ju Tsai; Yu-Te Liao; Nai-Chen Cheng 001; Yuan-Hua Chu; Yi-Hsing Tsai; Fang-Chu Chen; Tzi-cker Chiueh (DAC, 2016)

A Varactor-Based All-Digital Multi-Phase PLL with Random-Sampling Spur Suppression Techniques. - Chia-Wen Chang; Kai-Yu Lo; Hossameldin A. Ibrahim; Ming-Chiuan Su; Yuan-Hua Chu; Shyh-Jye Jou (IEICE Trans. Electron., 2016)

A 99.2% Tracking Accuracy Single-Inductor Quadruple-Input-Quadruple-Output Buck-Boost Converter Topology with Periodical Interval Perturbation and Observation MPPT. - Chao-Jen Huang; Yao-Sheng Ma; Wen-Hau Yang; Yen-Ting Lin; Chun-Chieh Kuo; Ke-Horng Chen; Hsiao-Jung Liu; Pei-Shan Yu; Fang-Chih Chu; Ching-Ju Lin; Hong-Wen Huang; Kuo-Chih Hung; et al. (A-SSCC, 2018)

A Wide-Range Capacitive DC-DC Converter with 2D-MPPT for Soil/Solar Energy Extraction. - I-Che Ou; Jia-Ping Yang; Chia-Hung Liu; Kai-Jie Huang; Kun-Ju Tsai; Yu Lee; Yuan-Hua Chu; Yu-Te Liao (A-SSCC, 2018)

MORAS: An energy-scalable system using adaptive voltage scaling. - Kuo-Chiang Chang; Shien-Chun Luo; Ching-Ji Huang; Jia-Hung Peng; Yuan-Hua Chu (VLSI-DAT, 2018)

A Sustainable Soil Energy Harvesting System With Wide-Range Power-Tracking Architecture. - I-Che Ou; Jia-Ping Yang; Chia-Hung Liu; Kai-Jie Huang; Kun-Ju Tsai; Yu Lee; Yuan-Hua Chu; Yu-Te Liao (IEEE Internet Things J., 2019)