Write Disturbance Modeling and Testing for MRAM. - Chin-Lung Su; Chih-Wea Tsai; Cheng-Wen Wu; Chien-Chung Hung; Young-Shying Chen; Ding-Yeong Wang; Yuan-Jen Lee; Ming-Jer Kao (IEEE Trans. Very Large Scale Integr. Syst., 2008)

Service Quality, Customer Satisfaction and Behavioral Intention in Shanghai Hospital Choice during the COVID-19 Pandemic. - Yuan-Jen Lee (IMMS, 2021)

15.9 A 16nm 16Mb Embedded STT-MRAM with a 20ns Write Time, a 1012 Write Endurance and Integrated Margin-Expansion Schemes. - Ku-Feng Lin; Hiroki Noguchi; Yi-Chun Shih; Perng-Fei Yuh; Yuan-Jen Lee; Tung-Cheng Chang; Sheng-Po Huang; Yu-Fan Lin; Chun-Ying Lee; Yen-Hsiang Huang; Jui-Che Tsai; Saman Adham; et al. (ISSCC, 2024)

Failure Mechanism and Unified Endurance Model of Embedded MRAM Towards Cache Application. - Y. H. Chen; Yu-Sheng Chen; Yi Ching Ong; Y. L. Chu; Kuo-Feng Huang; Yuan-Jen Lee; C. Y. Wang; C. Y. Wu; W. H. Chuang; Allen Y. J. Wang; K. C. Huang; Harry Chuang (IRPS, 2025)