Type-matching clock tree for zero skew clock gating. - Chia-Ming Chang 002; Shih-Hsu Huang; Yuan-Kai Ho; Jia-Zong Lin; Hsin-Po Wang 002; Yu-Sheng Lu (DAC, 2008)

Blockage-avoiding buffered clock-tree synthesis for clock latency-range and skew minimization. - Xin-Wei Shih; Chung-Chun Cheng; Yuan-Kai Ho; Yao-Wen Chang (ASP-DAC, 2010)

Obstacle-avoiding free-assignment routing for flip-chip designs. - Po-Wei Lee; Hsu-Chieh Lee; Yuan-Kai Ho; Yao-Wen Chang; Chen-Feng Chang; I-Jye Lin; Chin-Fang Shen (DAC, 2012)

Layer minimization in escape routing for staggered-pin-array PCBs. - Yuan-Kai Ho; Xin-Wei Shih; Yao-Wen Chang; Chung-Kuan Cheng (ASP-DAC, 2013)

Multiple chip planning for chip-interposer codesign. - Yuan-Kai Ho; Yao-Wen Chang (DAC, 2013)

Escape Routing for Staggered-Pin-Array PCBs. - Yuan-Kai Ho; Hsu-Chieh Lee; Yao-Wen Chang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013)

Obstacle-Avoiding Free-Assignment Routing for Flip-Chip Designs. - Yuan-Kai Ho; Hsu-Chieh Lee; Webber Lee; Yao-Wen Chang; Chen-Feng Chang; I-Jye Lin; Chin-Fang Shen (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014)