Restructure-Tolerant Timing Prediction via Multimodal Fusion. - Ziyi Wang 010; Siting Liu 002; Yuan Pu 001; Song Chen 001; Tsung-Yi Ho; Bei Yu 001 (DAC, 2023)

FastGR: Global Routing on CPU-GPU with Heterogeneous Task Graph Scheduler (Extended Abstract). - Siting Liu 002; Yuan Pu 001; Peiyu Liao; Hongzhong Wu; Rui Zhang; Zhitang Chen; Wenlong Lv; Yibo Lin; Bei Yu 001 (IJCAI, 2023)

FastGR: Global Routing on CPU-GPU With Heterogeneous Task Graph Scheduler. - Siting Liu 002; Yuan Pu 001; Peiyu Liao; Hongzhong Wu; Rui Zhang; Zhitang Chen; Wenlong Lv; Yibo Lin; Bei Yu 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

NeuroSelect: Learning to Select Clauses in SAT Solvers. - Hongduo Liu; Peng Xu; Yuan Pu 001; Lihao Yin; Hui-Ling Zhen; Mingxuan Yuan; Tsung-Yi Ho; Bei Yu 001 (DAC, 2024)

Lesyn: Placement-aware Logic Resynthesis for Non-Integer Multiple-Cell-Height Designs. - Yuan Pu 001; Fangzhou Liu; Yu Zhang 189; Zhuolun He; Yibo Lin; Kai-Yuan Chao; Bei Yu 001 (DAC, 2024)

Customized Retrieval Augmented Generation and Benchmarking for EDA Tool Documentation QA. - Yuan Pu 001; Zhuolun He; Tairu Qiu; Haoyuan Wu; Bei Yu 001 (ICCAD, 2024)

IncreMacro: Incremental Macro Placement Refinement. - Yuan Pu 001; Tinghuan Chen; Zhuolun He; Chen Bai; Haisheng Zheng; Yibo Lin; Bei Yu 001 (ISPD, 2024)

Multi-Electrostatics Based Placement for Non-Integer Multiple-Height Cells. - Yu Zhang 189; Yuan Pu 001; Fangzhou Liu; Peiyu Liao; Kai-Yuan Chao; Keren Zhu 001; Yibo Lin; Bei Yu 001 (ISPD, 2024)

Circuit Representation Learning with Masked Gate Modeling and Verilog-AIG Alignment. - Haoyuan Wu; Haisheng Zheng; Yuan Pu 001; Bei Yu 001 (ICLR, 2025)

HeLO: A Heterogeneous Logic Optimization Framework by Hierarchical Clustering and Graph Learning. - Yuan Pu 001; Fangzhou Liu; Zhuolun He; Keren Zhu 001; Rongliang Fu; Ziyi Wang 010; Tsung-Yi Ho; Bei Yu 001 (ISPD, 2025)

Large Language Models for EDA: From Assistants to Agents. - Zhuolun He; Yuan Pu 001; Haoyuan Wu; Yuhan Qiu; Tairu Qiu; Bei Yu 001 (Found. Trends Electron. Des. Autom., 2025)

ParSGCN: Bridging the Gap Between Emulation Partitioning and Scheduling. - Ziyi Wang 010; Wenqian Zhao; Yuan Pu 001; Lei Chen 031; Wilson W. K. Thong; Weihua Sheng; Tsung-Yi Ho; Bei Yu 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)

UniMoCo: Unified Modality Completion for Robust Multi-Modal Embeddings. - Jiajun Qin; Yuan Pu 001; Zhuolun He; Seunggeun Kim; David Z. Pan; Bei Yu 001 (CoRR, 2025)

EasyMRC: Efficient Mask Rule Checking via Representative Edge Sampling. - Jiahao Xu; Zhuolun He; Shuo Yin; Yuan Pu 001; Wenjian Yu; Bei Yu 001 (ACM Trans. Design Autom. Electr. Syst., 2025)

IncreMacro: Incremental Macro Placement Refinement. - Yuan Pu 001; Tinghuan Chen; Zhuolun He; Jiajun Qin; Chen Bai; Haisheng Zheng; Yibo Lin; Bei Yu 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)