A 4-Mb low-temperature DRAM. - Walter H. Henkels; Duen-Shun Wen; Rick L. Mohler; Robert L. Franch; Thomas J. Bucelot; Christopher W. Long; John A. Bracchitta; W. J. Cote; Gary B. Bronner; Yuan Taur; Robert H. Dennard (IEEE J. Solid State Circuits, 1991)

A half-micron CMOS logic generation. - Charles W. Koburger III; William F. Clark; James W. Adkisson; Eric Adler; Paul E. Bakeman; Albert S. Bergendahl; Alan B. Botula; W. Chang; Bijan Davari; John H. Givens; Howard H. Hansen; Steven J. Holmes; et al. (IBM J. Res. Dev., 1995)

CMOS scaling into the 21st century: 0.1 µm and beyond. - Yuan Taur; Yuh-Jier Mii; David J. Frank; H.-S. Philip Wong; Douglas A. Buchanan; Shalom J. Wind; Stephen A. Rishton; Watson A. Sai-Halasz; Edward J. Nowak (IBM J. Res. Dev., 1995)

CMOS scaling into the nanometer regime. - Yuan Taur; Douglas A. Buchanan; Wei Chen; David J. Frank; Khalid E. Ismail; Shih-Hsien Lo; George A. Sai-Halasz; Raman G. Viswanathan; Hsing-Jen C. Wann; Shalom J. Wind; Hon-Sum Philip Wong (Proc. IEEE, 1997)

4- and 13-GHz tuned amplifiers implemented in a 0.1-μm CMOS technology on SOI, SOS, and bulk substrates. - Yo-Chuol Ho; Kihong Kim; Brian A. Floyd; Clement Wann; Yuan Taur; Isaac Lagnado; Kenneth K. O (IEEE J. Solid State Circuits, 1998)

Modeling and characterization of quantization, polysilicon depletion, and direct tunneling effects in MOSFETs with ultrathin oxides. - Shih-Hsien Lo; Douglas A. Buchanan; Yuan Taur (IBM J. Res. Dev., 1999)

Transistors and IC design. - Yuan Taur (Adv. Comput., 2001)

Device scaling limits of Si MOSFETs and their application dependencies. - David J. Frank; Robert H. Dennard; Edward J. Nowak; Paul M. Solomon; Yuan Taur; Hon-Sum Philip Wong (Proc. IEEE, 2001)

Compact modeling of multiple-gate MOSFETs. - Yuan Taur; Jooyoung Song; Bo Yu (CICC, 2008)

A Review on Compact Modeling of Multiple-Gate MOSFETs. - Jooyoung Song; Bo Yu; Yu Yuan; Yuan Taur (IEEE Trans. Circuits Syst. I Regul. Pap., 2009)

Compact modeling of quantum effects in symmetric double-gate MOSFETs. - Wei Wang; Huaxin Lu; Jooyoung Song; Shih-Hsien Lo; Yuan Taur (Microelectron. J., 2010)

Determination of energy and spatial distribution of oxide border traps in In0.53Ga0.47As MOS capacitors from capacitance-voltage characteristics measured at various temperatures. - Chunmeng Dou; Dennis Lin; Abhitosh Vais; Tsvetan Ivanov; Han-Ping Chen; Koen Martens; Kuniyuki Kakushima; Hiroshi Iwai; Yuan Taur; Aaron Thean; Guido Groeseneken (Microelectron. Reliab., 2014)