Design of High-Performance Voltage Regulators Based on Frequency-Dependent Feedback Factor. - Liangguo Shen; Zushu Yan; Xing Zhang 002; Yuanfu Zhao; Yuan Wang 001 (ISCAS, 2007)

Low swing drivers based on charge redistribution. - Fengfeng Wu; Song Jia; Yuan Wang 001; Ganggang Zhang (Sci. China Inf. Sci., 2010)

A novel multi-finger layout strategy for GGnMOS ESD protection device. - Peng Zhang; Yuan Wang 001; Song Jia; Xing Zhang 002 (ASICON, 2011)

Novel single-loop multi-bit sigma-delta modulator using OTA sharing technique without DEM. - Hongyi Li; Yuan Wang 001; Song Jia; Xing Zhang 002 (IEICE Electron. Express, 2011)

Design of novel, semi-transparent flip-flops (STFF) for high speed and low power application. - Xiayu Li; Song Jia; Limin Liu; Yuan Wang 001; Ganggang Zhang (Sci. China Inf. Sci., 2012)

A Pulse-Generator-Free Hybrid Latch Based Flip-Flop (PHLFF). - Xiayu Li; Song Jia; Limin Liu; Yuan Wang 001 (IEICE Trans. Electron., 2012)

A novel dynamic element match technique in current-steering DAC. - Baoguang Liu; Yuan Wang 001; Guangliang Guo; Song Jia; Xing Zhang 002 (ASICON, 2013)

Novel gate-voltage-bias techniques for gate-coupled MOS (GCMOS) ESD protection circuits. - Guangyi Lu; Yuan Wang 001; Jian Cao 002; Song Jia; Ganggang Zhang; Xing Zhang 002 (ASICON, 2013)

A current mode sense amplifier with self-compensation circuit for SRAM application. - Heqing Xu; Song Jia; Jiyu Chen; Yuan Wang 001; Gang Du (ASICON, 2013)

Thermo data-weighted average dynamic element matching (DEM) encoder for current-steering DACs. - Yuan Wang 001; Baoguang Liu; Wei Su; Junlei Zhao; Xing Zhang 002 (IEICE Electron. Express, 2013)

Data Convertors Design for Optimization of the DDPL Family. - Song Jia; Li Liu; Xiayu Li; Fengfeng Wu; Yuan Wang 001; Ganggang Zhang (IEICE Trans. Electron., 2013)

A Current-Mirror Winner-Take-All Sense Amplifier for Low Voltage SRAMs. - Song Jia; Heqing Xu; Fengfeng Wu; Yuan Wang 001 (IEICE Trans. Electron., 2013)

Improved CRC Calculation Strategies for 64-bit Serial RapidIO. - Fengfeng Wu; Song Jia; Qinglong Meng; Shigong Lv; Yuan Wang 001; Dacheng Zhang (IEICE Trans. Electron., 2013)

Novel silicon-controlled rectifier (SCR) for digital and high-voltage ESD power supply clamp. - Peng Zhang; Yuan Wang 001; Xing Zhang 002; Xiaohua Ma 001; Yue Hao 001 (Sci. China Inf. Sci., 2014)

A low-leakage power clamp ESD protection circuit with prolonged ESD discharge time and compact detection network. - Jian Cao 002; Zhenxu Ye; Yuan Wang 001; Guangyi Lu; Xing Zhang 002 (ASICON, 2015)

A 10b, 0.7ps resolution coarse-fine time-to-digital converter in 65nm CMOS using a time residue amplifier. - Jiyu Chen; Song Jia; Yuan Wang 001 (ASICON, 2015)

Design on multi-bit adder using sense amplifier-based pass transistor logic for near-threshold voltage operation. - Fangyuan Dang; Yuan Wang 001; Yuequan Liu; Song Jia; Xing Zhang 002 (ASICON, 2015)

Four-bit transient-to-digital converter with a single RC-based detection circuit for system-level ESD protection. - Nan Han; Yuan Wang 001; Guangyi Lu; Jian Cao 002; Xing Zhang 002 (ASICON, 2015)

A low power and high speed CAM design using pulsed voltage for search-line. - Song Jia; Weiting Li; Wenyi Tang; Yuan Wang 001 (ASICON, 2015)

A reference-less all-digital burst-mode CDR with embedded TDC. - Mengyin Jiang; Yuan Wang 001; Baoguang Liu; Yuequan Liu; Song Jia; Xing Zhang 002 (ASICON, 2015)

A low-power high-speed 32/33 prescaler based on novel divide-by-4/5 unit with improved true single-phase clock logic. - Song Jia; Shilin Yan; Yuan Wang 001; Ganggang Zhang (ISCAS, 2015)

180.5Mbps-8Gbps DLL-based clock and data recovery circuit with low jitter performance. - Yuequan Liu; Yuan Wang 001; Song Jia; Xing Zhang 002 (ISCAS, 2015)

Investigation on the layout strategy of ggNMOS ESD protection devices for uniform conduction behavior and optimal width scaling. - Guangyi Lu; Yuan Wang 001; Lizhong Zhang; Jian Cao 002; Song Jia; Xing Zhang 002 (Sci. China Inf. Sci., 2015)

Novel DEM Technique for Current-Steering DAC in 65-nm CMOS Technology. - Yuan Wang 001; Wei Su; Guangliang Guo; Xing Zhang 002 (IEICE Trans. Electron., 2015)

A novel low-power and high-speed dual-modulus prescaler based on extended true single-phase clock logic. - Song Jia; Ziyi Wang; Zijin Li; Yuan Wang 001 (ISCAS, 2016)

A novel low-leakage power-rail ESD clamp circuit with adjustable triggering voltage and superior false-triggering immunity for nanoscale applications. - Guangyi Lu; Yuan Wang 001; Jian Cao 002; Song Jia; Xing Zhang 002 (ISCAS, 2016)

Delay-locked loop based frequency quadrupler with wide operating range and fast locking characteristics. - Yuan Wang 001; Yuequan Liu; Mengyin Jiang; Song Jia; Xing Zhang 002 (ISCAS, 2016)

A compact SCR model using advanced BJT models and standard SPICE elements. - Jian Cao 002; Jingya Xu; Yuan Wang 001; Guangyi Lu; Xing Zhang 002 (Sci. China Inf. Sci., 2016)

Design of a novel static-triggered power-rail ESD clamp circuit in a 65-nm CMOS process. - Guangyi Lu; Yuan Wang 001; Lizhong Zhang; Jian Cao 002; Xing Zhang 002 (Sci. China Inf. Sci., 2016)

Area-efficient transient power-rail electrostatic discharge clamp circuit with mis-triggering immunity in a 65-nm CMOS process. - Yuan Wang 001; Guangyi Lu; Haibing Guo; Jian Cao 002; Song Jia; Xing Zhang 002 (Sci. China Inf. Sci., 2016)

A novel SPICE circuit model of electrostatic discharge (ESD) generator. - Jian Cao 002; Yize Wang; Yuan Wang 001; Guangyi Lu; Xing Zhang 002 (IEICE Electron. Express, 2016)

Optimization on Layout Strategy of Gate-Grounded NMOS for On-Chip ESD Protection in a 65-nm CMOS Process. - Guangyi Lu; Yuan Wang 001; Xing Zhang 002 (IEICE Trans. Electron., 2016)

A Short-Time Three-Phase Single-Rail Precharge Logic against Differential Power Analysis. - Wenyi Tang; Song Jia; Yuan Wang 001 (IEICE Trans. Electron., 2016)

A true single-phase clock dual-modulus prescaler with enhanced robustness against leakage currents. - Song Jia; Ziyi Wang; Shilin Yan; Yuan Wang 001 (Int. J. Circuit Theory Appl., 2016)

A 4.8-6.8 GHz low phase noise LC VCO in 0.13-µm CMOS technology. - Yuan Wang 001; Shanliang Gan; Song Jia; Xing Zhang 002 (Int. J. Circuit Theory Appl., 2016)

A novel equivalent circuit model of the surge wave generator. - Yukuai Chen; Jian Cao 002; Zhang Qihui; Yuan Wang 001; Xing Zhang 002 (ASICON, 2017)

Power-rail ESD clamp circuit with hybrid-detection enhanced triggering in a 65-nm, 1.2-V CMOS process. - Guangyi Lu; Yuan Wang 001; Yize Wang; Xing Zhang 002 (ISCAS, 2017)

A reliable true random number generator based on novel chaotic ring oscillator. - Yunfan Yang; Song Jia; Yuan Wang 001; Shaonan Zhang; Chao Liu (ISCAS, 2017)

Compact digital-controlled neuromorphic circuit with low power consumption. - Jin Zhang; Yuan Wang 001; Xing Zhang 002; Ru Huang 001 (ISCAS, 2017)

A novel TLP-based method to deliver IEC 61000-4-2 ESD stress. - Yize Wang; Yuan Wang 001; Guangyi Lu; Jian Cao 002; Xing Zhang 002 (IEICE Electron. Express, 2017)

Power-Rail ESD Clamp Circuit with Parasitic-BJT and Channel Parallel Shunt Paths to Achieve Enhanced Robustness. - Yuan Wang 001; Guangyi Lu; Yize Wang; Xing Zhang 002 (IEICE Trans. Electron., 2017)

Delay-locked loop based clock and data recovery with wide operating range and low jitter in a 65-nm CMOS process. - Yuan Wang 001; Yuequan Liu; Song Jia; Xing Zhang 002 (Int. J. Circuit Theory Appl., 2017)

A Compact and Accelerated Spike-based Neuromorphic VLSI Chip for Pattern Recognition. - Cheng Li; Yuan Wang 001; Jin Zhang; Xiaoxin Cui; Ru Huang 001 (BioCAS, 2018)

Investigation on the Gate Bias Voltage of BigFET in Power-rail ESD Clamp Circuit for Enhanced Transient Noise Immunity. - Guangyi Lu; Yuan Wang 001; Lizhong Zhang; Yize Wang; Ru Huang 001; Xing Zhang 002 (ISCAS, 2018)

A Multi-Mode Silicon Neuron Circuit With High Robustness Against PVT Variation. - Lu Zhang; Jin Zhang; Yuan Wang 001; Xing Zhang 002; Ru Huang 001 (ISCAS, 2018)

A 1-Gbps reference-less burst-mode CDR with embedded TDC in a 65-nm CMOS process. - Yuan Wang 001; Mengyin Jiang; Baoguang Liu; Song Jia; Xing Zhang 002 (Int. J. Circuit Theory Appl., 2018)

An Energy-Efficient Mixed-Signal Parallel Multiply-Accumulate (MAC) Engine Based on Stochastic Computing. - Xinyue Zhang 002; Jiahao Song; Yuan Wang 001; Yawen Zhang; Zuodong Zhang; Runsheng Wang; Ru Huang 001 (ASICON, 2019)

An Energy-Efficient Computing-in-Memory Neuromorphic System with On-Chip Training. - Zhao Zhao; Yuan Wang 001; Xinyue Zhang 002; Xiaoxin Cui; Ru Huang 001 (BioCAS, 2019)

Memory System Designed for Multiply-Accumulate (MAC) Engine Based on Stochastic Computing. - Xinyue Zhang 002; Yuan Wang 001; Yawen Zhang; Jiahao Song; Zuodong Zhang; Kaili Cheng; Runsheng Wang; Ru Huang 001 (ICICDT, 2019)

A Sparse Event-Driven Unsupervised Learning Network with Adaptive Exponential Integrate-and-Fire Model. - Zhao Zhao; Yuan Wang 001; Cheng Li; Xiaoxin Cui; Ru Huang 001 (ICICDT, 2019)

A Survey of Computation-Driven Data Encoding. - Weikang Qian; Runsheng Wang; Yuan Wang 001; Marc D. Riedel; Ru Huang 001 (SiPS, 2019)

Parallel Convolutional Neural Network (CNN) Accelerators Based on Stochastic Computing. - Yawen Zhang; Xinyue Zhang 002; Jiahao Song; Yuan Wang 001; Ru Huang 001; Runsheng Wang (SiPS, 2019)

Improved turn-on behavior in a diode-triggered silicon-controlled rectifier for high-speed electrostatic discharge protection. - Lizhong Zhang; Yuan Wang 001; Yize Wang; Xing Zhang 002; Yandong He (Sci. China Inf. Sci., 2019)

A Parallel Bitstream Generator for Stochastic Computing. - Yawen Zhang; Runsheng Wang; Xinyue Zhang 002; Zherui Zhang; Jiahao Song; Zuodong Zhang; Yuan Wang 001; Ru Huang 001 (CoRR, 2019)

When Sorting Network Meets Parallel Bitstreams: A Fault-Tolerant Parallel Ternary Neural Network Accelerator based on Stochastic Computing. - Yawen Zhang; Sheng Lin 001; Runsheng Wang; Yanzhi Wang; Yuan Wang 001; Weikang Qian; Ru Huang 001 (DATE, 2020)

Accurate and Energy-Efficient Implementation of Non-Linear Adder in Parallel Stochastic Computing using Sorting Network. - Yawen Zhang; Runsheng Wang; Yixuan Hu; Weikang Qian; Yanzhi Wang; Yuan Wang 001; Ru Huang 001 (ISCAS, 2020)

A New Behavioral Model of Gate-Grounded NMOS for Simulating Snapback Characteristics. - Yize Wang; Guangyi Lu; Yuan Wang 001 (IEEE Access, 2020)

Parallel Hybrid Stochastic-Binary-Based Neural Network Accelerators. - Yawen Zhang; Runsheng Wang; Xinyue Zhang 002; Yuan Wang 001; Ru Huang 001 (IEEE Trans. Circuits Syst., 2020)

A 16Kb Transpose 6T SRAM In-Memory-Computing Macro based on Robust Charge-Domain Computing. - Jiahao Song; Yuan Wang 001; Xiyuan Tang; Runsheng Wang; Ru Huang 001 (A-SSCC, 2021)

A 28-nm 0.34-pJ/SOP Spike-Based Neuromorphic Processor for Efficient Artificial Neural Network Implementations. - Yisong Kuang; Xiaoxin Cui; Yi Zhong; Kefei Liu 002; Chenglong Zou; Zhenhui Dai; Dunshan Yu; Yuan Wang 001; Ru Huang 001 (ISCAS, 2021)

A Spike-Event-Based Neuromorphic Processor with Enhanced On-Chip STDP Learning in 28nm CMOS. - Yi Zhong; Xiaoxin Cui; Yisong Kuang; Kefei Liu 002; Yuan Wang 001; Ru Huang 001 (ISCAS, 2021)

Suppressing the endemic equilibrium in SIS epidemics: A state dependent approach. - Yuan Wang 001; Sebin Gracy; Hideaki Ishii; Karl Henrik Johansson (CoRR, 2021)

Integer-Only Neural Network Quantization Scheme Based on Shift-Batch-Normalization. - Qingyu Guo; Yuan Wang 001; Xiaoxin Cui (CoRR, 2021)

TD-SRAM: Time-Domain-Based In-Memory Computing Macro for Binary Neural Networks. - Jiahao Song; Yuan Wang 001; Minguang Guo; Xiang Ji; Kaili Cheng; Yixuan Hu; Xiyuan Tang; Runsheng Wang; Ru Huang 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

A 64K-Neuron 64M-1b-Synapse 2.64pJ/SOP Neuromorphic Chip With All Memory on Chip for Spike-Based Models in 65nm CMOS. - Yisong Kuang; Xiaoxin Cui; Yi Zhong; Kefei Liu 002; Chenglong Zou; Zhenhui Dai; Yuan Wang 001; Dunshan Yu; Ru Huang 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

Boosting Dense Long-Tailed Object Detection from Data-Centric View. - Weichen Xu 001; Jian Cao 002; Tianhao Fu; Hongyi Yao; Yuan Wang 001 (ACCV (3), 2022)

A Mapping Model of SNNs to Neuromorphic Hardware. - Xiuping Cui; Xiaochen Hao; Yun Liang 001; Guangyu Sun 003; Xiaoxin Cui; Yuan Wang 001; Ru Huang 001 (AICAS, 2022)

A Full-Neuron Memory Model Designed for Neuromorphic Systems. - Kefei Liu 002; Xiaoxin Cui; Chenglong Zou; Yisong Kuang; Yi Zhong; Kanglin Xiao; Yuan Wang 001 (AICAS, 2022)

A Hybrid Spiking Recurrent Neural Network on Hardware for Efficient Emotion Recognition. - Chenglong Zou; Xiaoxin Cui; Yisong Kuang; Yuan Wang 001; Xinan Wang (AICAS, 2022)

A Sample-Based Algorithm for Approximately Testing r-Robustness of a Digraph. - Yuhao Yi; Yuan Wang 001; Xingkang He; Stacy Patterson; Karl Henrik Johansson (CDC, 2022)

An Once-for-All Budgeted Pruning Framework for ConvNets Considering Input Resolution. - Wenyu Sun; Jian Cao 002; Pengtao Xu; Xiangcheng Liu; Yuan Zhang 020; Yuan Wang 001 (CVPR Workshops, 2022)

A Reconfigurable SRAM Computing-in-Memory Macro Supporting Ping-Pong Operation and CIM pipeline for Multi-mode MAC operations. - Kanglin Xiao; Xiaoxin Cui; Xin Qiao; Xin'an Wang; Yuan Wang 001 (ICTA, 2022)

A 4-bit Integer-Only Neural Network Quantization Method Based on Shift Batch Normalization. - Qingyu Guo; Xiaoxin Cui; Jian Zhang; Aifei Zhang; Xinjie Guo; Yuan Wang 001 (ISCAS, 2022)

An Event-driven Spiking Neural Network Accelerator with On-chip Sparse Weight. - Yisong Kuang; Xiaoxin Cui; Chenglong Zou; Yi Zhong; Zhenhui Dai; Zilin Wang; Kefei Liu 002; Dunshan Yu; Yuan Wang 001 (ISCAS, 2022)

A 28nm 64Kb SRAM based Inference-Training Tri-Mode Computing-in-Memory Macro. - Nanbing Pan; Xiaoxin Cui; Xin Qiao; Kanglin Xiao; Qingyu Guo; Yuan Wang 001 (ISCAS, 2022)

A Novel Low-Leakage ESD Power Clamp Circuit with Adjustable Transient Response Time. - Zilong Shen; Yize Wang; Xing Zhang 002; Yuan Wang 001 (ISCAS, 2022)

A Computing-in-Memory SRAM Macro Based on Fully-Capacitive-Coupling With Hierarchical Capacity Attenuator for 4-b MAC Operation. - Kanglin Xiao; Xiaoxin Cui; Xin Qiao; Nanbing Pan; Xin'an Wang; Yuan Wang 001 (ISCAS, 2022)

A State Feedback Controller for Mitigation of Continuous-Time Networked SIS Epidemics. - Yuan Wang 001; Sebin Gracy; César A. Uribe; Hideaki Ishii; Karl Henrik Johansson (CoRR, 2022)

A 128 Kb DAC-less 6T SRAM computing-in-memory macro with prioritized subranging ADC for AI edge applications. - Kanglin Xiao; Xiaoxin Cui; Xin Qiao; Xin'an Wang; Yuan Wang 001 (Microelectron. J., 2022)

Modular building blocks for mapping spiking neural networks onto a programmable neuromorphic processor. - Chenglong Zou; Xiaoxin Cui; Guang Chen; Shuo Feng; Kefei Liu 002; Xinan Wang; Yuan Wang 001 (Microelectron. J., 2022)

A 65 nm 73 kb SRAM-Based Computing-In-Memory Macro With Dynamic-Sparsity Controlling. - Xin Qiao; Jiahao Song; Xiyuan Tang; Haoyang Luo; Nanbing Pan; Xiaoxin Cui; Runsheng Wang; Yuan Wang 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

A Scalable Model for Snapback Characteristics of Circuit-Level ESD Simulation. - Zilong Shen; Yize Wang; Yunhao Li; Xing Zhang 002; Yuan Wang 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

ESSA: Design of a Programmable Efficient Sparse Spiking Neural Network Accelerator. - Yisong Kuang; Xiaoxin Cui; Zilin Wang; Chenglong Zou; Yi Zhong; Kefei Liu 002; Zhenhui Dai; Dunshan Yu; Yuan Wang 001; Ru Huang 001 (IEEE Trans. Very Large Scale Integr. Syst., 2022)

Unsupervised Learning of Spike-Timing-Dependent Plasticity Based on a Neuromorphic Implementation. - Yi Zhong; Zilin Wang; Xiaoxin Cui; Jian Cao 002; Yuan Wang 001 (AICAS, 2023)

An Efficient Spiking Neural Network Accelerator with Sparse Weight. - Zilin Wang; Yi Zhong; Youming Yang 002; Xiaoxin Cui; Yuan Wang 001 (BioCAS, 2023)

A 9.7fJ/Conv.-Step Capacitive Sensor Readout Circuit with Incremental Zoomed Time Domain Quantization. - Zilong Shen; Xiyuan Tang; Zhongyi Wu; Haoyang Luo; Zongnan Wang; Mingjie Liu; Xing Zhang 002; Yuan Wang 001 (CICC, 2023)

A Calibration-Free 15-level/Cell eDRAM Computing-in-Memory Macro with 3T1C Current-Programmed Dynamic-Cascoded MLC achieving 233-to-304-TOPS/W 4b MAC. - Jiahao Song; Xiyuan Tang; Haoyang Luo; Haoyi Zhang; Xin Qiao; Zixuan Sun; Xiangxing Yang; Yuan Wang 001; Runsheng Wang; Ru Huang 001 (CICC, 2023)

Efficient Non-Linear Adder for Stochastic Computing with Approximate Spatial-Temporal Sorting Network. - Yixuan Hu; Tengyu Zhang; Meng Li 004; Renjie Wei; Liangzhen Lai; Yuan Wang 001; Runsheng Wang; Ru Huang 001 (DAC, 2023)

Accurate yet Efficient Stochastic Computing Neural Acceleration with High Precision Residual Fusion. - Yixuan Hu; Tengyu Zhang; Renjie Wei; Meng Li 004; Runsheng Wang; Yuan Wang 001; Ru Huang 001 (DATE, 2023)

Linear Leakage: Better Robustness for Spiking Neural Network. - Jinming Che; Jian Cao 002; Shuo Feng; Jue Chen; Yuan Wang 001 (ICACT, 2023)

Razor SNN: Efficient Spiking Neural Network with Temporal Embeddings. - Yuan Zhang 020; Jian Cao 002; Jue Chen; Wenyu Sun; Yuan Wang 001 (ICANN (5), 2023)

Monad: Towards Cost-Effective Specialization for Chiplet-Based Spatial Accelerators. - Xiaochen Hao; Zijian Ding; Jieming Yin; Yuan Wang 001; Yun Liang 001 (ICCAD, 2023)

Channel Pruning Via Attention Module And Memory Curve. - Hufei Li; Jian Cao 002; Xiangcheng Liu; Jue Chen; Jingjie Shang; Yu Qian; Yuan Wang 001 (ICIP, 2023)

A New ANN-SNN Conversion Method with High Accuracy, Low Latency and Good Robustness. - Bingsen Wang; Jian Cao 002; Jue Chen; Shuo Feng; Yuan Wang 001 (IJCAI, 2023)

A Spiking Neural Network Accelerator based on Ping-Pong Architecture with Sparse Spike and Weight. - Zilin Wang; Yi Zhong; Xiaoxin Cui; Yisong Kuang; Yuan Wang 001 (ISCAS, 2023)

A 28nm 38-to-102-TOPS/W 8b Multiply-Less Approximate Digital SRAM Compute-In-Memory Macro for Neural-Network Inference. - Yifan He 003; Haikang Diao; Chen Tang; Wenbin Jia; Xiyuan Tang; Yuan Wang 001; Jinshan Yue; Xueqing Li 002; Huazhong Yang; Hongyang Jia; Yongpan Liu (ISSCC, 2023)

A 150kHz-BW 15-ENOB Incremental Zoom ADC with Skipped Sampling and Single Buffer Embedded Noise-Shaping SAR Quantizer. - Zongnan Wang; Lu Jie 001; Zichen Kong; Mingtao Zhan; Yi Zhong; Yuan Wang 001; Xiyuan Tang (ISSCC, 2023)

ALEGO: Towards Cost-Aware Architecture and Integration Co-Design for Chiplet-based Spatial Accelerators. - Xiaochen Hao; Zijian Ding; Jieming Yin; Yuan Wang 001; Yun Liang 001 (CoRR, 2023)

Multi-Competitive Virus Spread over a Time-Varying Networked SIS Model with an Infrastructure Network. - Sebin Gracy; Yuan Wang 001; Philip E. Pare; César A. Uribe (CoRR, 2023)

Razor SNN: Efficient Spiking Neural Network with Temporal Embeddings. - Yuan Zhang 020; Jian Cao 002; Ling Zhang; Jue Chen; Wenyu Sun; Yuan Wang 001 (CoRR, 2023)

Real-Time Target Tracking System With Spiking Neural Networks Implemented on Neuromorphic Chips. - Kefei Liu 002; Xiaoxin Cui; Xiang Ji; Yisong Kuang; Chenglong Zou; Yi Zhong; Kanglin Xiao; Yuan Wang 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

A 28 nm 16 Kb Bit-Scalable Charge-Domain Transpose 6T SRAM In-Memory Computing Macro. - Jiahao Song; Xiyuan Tang; Xin Qiao; Yuan Wang 001; Runsheng Wang; Ru Huang 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

A 28nm 32Kb SRAM Computing-in-Memory Macro With Hierarchical Capacity Attenuator and Input Sparsity-Optimized ADC for 4b Mac Operation. - Kanglin Xiao; Xiaoxin Cui; Xin Qiao; Jiahao Song; Haoyang Luo; Xin'an Wang; Yuan Wang 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

An Efficient Neuromorphic Implementation of Temporal Coding-Based On-Chip STDP Learning. - Yi Zhong; Zilin Wang; Xiaoxin Cui; Jian Cao 002; Yuan Wang 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

Toward a Lossless Conversion for Spiking Neural Networks with Negative-Spike Dynamics. - Chenglong Zou; Xiaoxin Cui; Guang Chen; Yuanyuan Jiang; Yuan Wang 001 (Adv. Intell. Syst., 2023)

On-Chip Incremental Learning based on Unsupervised STDP Implementation. - Guang Chen; Jian Cao 002; Shuo Feng; Zilin Wang; Yi Zhong; Qibin Li; Xiongbo Zhao; Xing Zhang 002; Yuan Wang 001 (AICAS, 2024)

A Hybrid Heterogeneous Neural Network Accelerator based on Systolic Array. - Zilin Wang; Yi Zhong; Guang Chen; Shuo Feng; Youming Yang 002; Xiaoxin Cui; Yuan Wang 001 (AICAS, 2024)

An Efficient Spiking Convolutional Architecture with Compressed Address Event Representation and Adaptive Delay Asynchronous Clocks. - Zhenhui Dai; Li Lun; Zilin Wang; Jiawei Wang; Kunyu Feng; Yuan Wang 001; Dunshan Yu; Xiaoxin Cui (BioCAS, 2024)

A 28nm 128TFLOPS/W Computing-In-Memory Engine Supporting One-Shot Floating-Point NN Inference and On-Device Fine-Tuning for Edge AI. - Haikang Diao; Haoyang Luo; Jiahao Song; Bocheng Xu; Runsheng Wang; Yuan Wang 001; Xiyuan Tang (CICC, 2024)

MixCIM: A Hybrid-Cell-Based Computing-in-Memory Macro with Less-Data-Movement and Activation-Memory-Reuse for Depthwise Separable Neural Networks. - Xin Qiao; Jiahao Song; Youming Yang 002; Renjie Wei; Xiyuan Tang; Meng Li 004; Runsheng Wang; Yuan Wang 001 (CICC, 2024)

A 181.8dB FoMs Zoom Capacitance-to-Digital Converter with kT/C Noise Cancellation and Dead Band Operation. - Zilong Shen; Jiaiun Tang; Haoyang Luo; Zhongyi Wu; Zongnan Wang; Xing Zhang 002; Xiyuan Tang; Yuan Wang 001 (CICC, 2024)

PVTSizing: A TuRBO-RL-Based Batch-Sampling Optimization Framework for PVT-Robust Analog Circuit Synthesis. - Zichen Kong; Xiyuan Tang; Wei Shi 011; Yiheng Du; Yibo Lin; Yuan Wang 001 (DAC, 2024)

ASCEND: Accurate yet Efficient End-to-End Stochastic Computing Acceleration of Vision Transformer. - Tong Xie; Yixuan Hu; Renjie Wei; Meng Li 004; Yuan Wang 001; Runsheng Wang; Ru Huang 001 (DATE, 2024)

HG-PIPE: Vision Transformer Acceleration with Hybrid-Grained Pipeline. - Qingyu Guo; Jiayong Wan; Songqiang Xu; Meng Li 004; Yuan Wang 001 (ICCAD, 2024)

OSCA: End-to-end Serial Stochastic Computing Neural Acceleration with Fine-grained Scaling and Piecewise Activation. - Yixuan Hu; Yikang Jia; Meng Li 004; Yuan Wang 001; Runsheng Wang; Ru Huang 001 (ICCAD, 2024)

AdapMoE: Adaptive Sensitivity-based Expert Gating and Management for Efficient MoE Inference. - Shuzhang Zhong; Ling Liang; Yuan Wang 001; Runsheng Wang; Ru Huang 001; Meng Li 004 (ICCAD, 2024)

An Energy-Efficient Differential Frame Convolutional Accelerator with on-Chip Fusion Storage Architecture and Pixel-Level Pipeline Data Flow. - Zhenhui Dai; Jiawei Wang; Yi Zhong; Kunyu Feng; Cheng Zhao; Yuanyuan Jiang; Peiyu Chen; Yuan Wang 001; Dunshan Yu; Xiaoxin Cui (ISCAS, 2024)

An End-to-End SoC for Brain-Inspired CNN-SNN Hybrid Applications. - Zhaotong Zhang; Yi Zhong; Yingying Cui; Yawei Ding; Yukun Xue; Qibin Li; Ruining Yang; Jian Cao 002; Yuan Wang 001 (ISCAS, 2024)

A cascaded timestamp-free event camera image compression method for gesture recognition. - Lindong Wu; Xuefei Lv; Shaoning Jin; Chaoyi Ban; Zongwei Wang 001; Yuan Wang 001; Yimao Cai (ISIE, 2024)

30.5 A Variation-Tolerant In-eDRAM Continuous-Time Ising Machine Featuring 15-Level Coefficients and Leaked Negative-Feedback Annealing. - Jiahao Song; Zihan Wu 005; Xiyuan Tang; Bocheng Xu; Haoyang Luo; Youming Yang 002; Yuan Wang 001; Runsheng Wang; Ru Huang 001 (ISSCC, 2024)

Investigation and mitigation of Mott neuronal oscillation fluctuation in spiking neural network. - Lindong Wu; Zongwei Wang 001; Lin Bao; Linbo Shan; Zhizhen Yu; Yunfan Yang; Shuangjie Zhang; Guandong Bai; Cuimei Wang; John Robertson; Yuan Wang 001; Yimao Cai; et al. (Sci. China Inf. Sci., 2024)

A 4-bit Calibration-Free Computing-In-Memory Macro With 3T1C Current-Programed Dynamic-Cascode Multi-Level-Cell eDRAM. - Jiahao Song; Xiyuan Tang; Haoyang Luo; Haoyi Zhang; Xin Qiao; Zixuan Sun; Xiangxing Yang; Zihan Wu 005; Yuan Wang 001; Runsheng Wang; Ru Huang 001 (IEEE J. Solid State Circuits, 2024)

A 16.38TOPS and 4.55POPS/W SRAM Computing-in-Memory Macro for Signed Operands Computation and Batch Normalization Implementation. - Xin Qiao; Qingyu Guo; Xiyuan Tang; Jiahao Song; Renjie Wei; Meng Li 004; Runsheng Wang; Yuan Wang 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

OASIS: A 28-nm 32-kb SRAM-Based Computing-in-Memory Design With Output Activation Sparsity Support. - Qingyu Guo; Nanbing Pan; Xin Qiao; Xiaoxin Cui; Yuan Wang 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

An eDRAM-Based Computing-in-Memory Macro With Full-Valid-Storage and Channel-Wise-Parallelism for Depthwise Neural Network. - Xin Qiao; Youming Yang 002; Chang Xue; Yandong He; Xiaoxin Cui; Song Jia; Yuan Wang 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

A 768.7-2124.2 TOPS/W Time-Domain Computing-in-Memory Macro With Low Static Leakage and Precision-Configurable TDC. - Chang Xue; Xin Qiao; Xu Ren; Gang Du; Yuan Wang 001; Yandong He (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

How the Brain Achieves Real-Time Vision: A Spiking Position Perception Model. - Kefei Liu 002; Jingjie Shang; Xiaoxin Cui; Chenglong Zou; Yisong Kuang; Kanglin Xiao; Yi Zhong; Yuan Wang 001 (IEEE Trans. Cogn. Dev. Syst., 2024)

A 28nm 8Kb Reconfigurable SRAM Computing-In-Memory Macro With Input-Sparsity Optimized DTC for Multi-Mode MAC Operations. - Kanglin Xiao; Xin Qiao; Xiaoxin Cui; Jiahao Song; Haoyang Luo; Xin'an Wang; Yuan Wang 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

BrainQN: Enhancing the Robustness of Deep Reinforcement Learning with Spiking Neural Networks. - Shuo Feng; Jian Cao 002; Zehong Ou; Guang Chen; Yi Zhong; Zilin Wang; Juntong Yan; Jue Chen; Bingsen Wang; Chenglong Zou; Zebang Feng; Yuan Wang 001 (Adv. Intell. Syst., 2024)

CASCADE: A Framework for CNN Accelerator Synthesis With Concatenation and Refreshing Dataflow. - Qingyu Guo; Haoyang Luo; Meng Li 004; Xiyuan Tang; Yuan Wang 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

NeuroREC: A 28-nm Efficient Neuromorphic Processor for Radar Emitter Classification. - Zilin Wang; Zehong Ou; Yi Zhong; Youming Yang 002; Li Lun; Hufei Li; Jian Cao 002; Xiaoxin Cui; Song Jia; Yuan Wang 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

A 266F2 Ultra Stable Differential NOR-Structured Physically Unclonable Function With < 6x10-9 Bit Error Rate Through Efficient Redundancy Strategy. - Haoyi Zhang; Jiahao Song; Haoyang Luo; Xiyuan Tang; Yuan Wang 001; Runsheng Wang; Ru Huang 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

Marmotini: A Weight Density Adaptation Architecture With Hybrid Compression Method for Spiking Neural Network. - Zilin Wang; Yi Zhong; Zehong Ou; Youming Yang 002; Shuo Feng; Guang Chen; Xiaoxin Cui; Song Jia; Yuan Wang 001 (IEEE Trans. Very Large Scale Integr. Syst., 2024)

A 4.82-µW 183.4dB-FoMSNDR CT Incremental Tracking-Zoom Sensor Readout Frontend with Floating-Gm-CCO Integrator. - Haoyang Luo; Zongnan Wang; Jiarui Wang; Bingrui Li; Zilong Shen; Yang Liu; Xiaojie Duan; Yuan Wang 001; Xiyuan Tang (CICC, 2025)

Towards Effective and Sparse Adversarial Attack on Spiking Neural Networks via Breaking Invisible Surrogate Gradients. - Li Lun; Kunyu Feng; Qinglong Ni; Ling Liang; Yuan Wang 001; Ying Li 056; Dunshan Yu; Xiaoxin Cui (CVPR, 2025)

SEGA-DCIM: Design Space Exploration-Guided Automatic Digital CIM Compiler with Multiple Precision Support. - Haikang Diao; Haoyi Zhang; Jiahao Song; Haoyang Luo; Yibo Lin; Runsheng Wang; Yuan Wang 001; Xiyuan Tang (DATE, 2025)

FLASH: An Efficient Hardware Accelerator Leveraging Approximate and Sparse FFT for Homomorphic Encryption. - Tengyu Zhang; Yufei Xue; Ling Liang; Zhen Gu; Yuan Wang 001; Runsheng Wang; Ru Huang 001; Meng Li 004 (DATE, 2025)

NeuroHexa: A 2D/3D-Scalable Model-Adaptive NoC Architecture for Neuromorphic Computing. - Yi Zhong; Zilin Wang; Yipeng Gao; Xiaoxin Cui; Xing Zhang 002; Yuan Wang 001 (DATE, 2025)

CROSSCUT: A Multi-Core Neuromorphic Accelerator Improving Resource-Utilization. - Youming Yang 002; Yi Zhong; Zilin Wang; Tao Zhang; Li Lun; Yingying Cui; Xiaoxin Cui; Song Jia; Yuan Wang 001 (ISCAS, 2025)

Enabling Fault Isolation in Fault Injection for Automotive-grade Circuits Simulation. - Yulong Liu; Junhao Lin; Yuheng Li; Pingsheng Zhang; Zenan Yan; Yuan Wang 001; Song Jia (ISCAS, 2025)

HyNITA: A Neuromorphic Inference and Training Accelerator for Hybrid ANN-SNN Fusion Models. - Yi Zhong; Li Lun; Zilin Wang; Jinhao Ruan; Yipeng Gao; Xiaoxin Cui; Xing Zhang 002; Yuan Wang 001 (ISCAS, 2025)

A 185.2dB-FoMs 8.7aFrms Zoomed Capacitance-to-Digital Converter with Chopping-Based kT/C Noise Cancellation and Add-Then-Subtract Phase-Domain Lead-Compensation Technique. - Bingrui Li; Zilong Shen; Haoyang Luo; Jiachang Yang; Zongnan Wang; Yuan Wang 001; Xiyuan Tang (ISSCC, 2025)

A 184.8dB-FoMs 1.6MS/s Incremental Noise-Shaping Pipeline ADC with Single-Amplification-Based kT/C Noise Cancellation Technique. - Zongnan Wang; Bingrui Li; Jiajun Tang; Zhongyi Wu; Haoyang Luo; Yuan Wang 001; Xiyuan Tang (ISSCC, 2025)

37.5 SKADI: A 28nm Complete K-SAT Solver Featuring Dual-Path SRAM-Based Macro and Incremental Update with 100% Solvability. - Zihan Wu 005; Xiyuan Tang; Tao Zhang; Lishan Lin; Haoyang Luo; Bocheng Xu; Zhongyi Wu; Jiahao Song; Yitao Liang; Xiaochen Bo; Yuan Wang 001 (ISSCC, 2025)

LightMamba: Efficient Mamba Acceleration on FPGA with Quantization and Hardware Co-design. - Renjie Wei; Songqiang Xu; Linfeng Zhong; Zebin Yang; Qingyu Guo; Yuan Wang 001; Runsheng Wang; Meng Li 004 (CoRR, 2025)

A Multiply-Less Approximate SRAM Compute-In-Memory Macro for Neural-Network Inference. - Haikang Diao; Yifan He 003; Xuan Li; Chen Tang; Wenbin Jia; Jinshan Yue; Haoyang Luo; Jiahao Song; Xueqing Li 002; Huazhong Yang; Hongyang Jia; Yongpan Liu; et al. (IEEE J. Solid State Circuits, 2025)

PAICORE: A 1.9-Million-Neuron 5.181-TSOPS/W Digital Neuromorphic Processor With Unified SNN-ANN and On-Chip Learning Paradigm. - Yi Zhong; Yisong Kuang; Kefei Liu 002; Zilin Wang; Shuo Feng; Guang Chen; Youming Yang 002; Xiuping Cui; Qiankun Wang; Jian Cao 002; Song Jia; Yun Liang 001; et al. (IEEE J. Solid State Circuits, 2025)

ReaLM: Reliable and Efficient Large Language Model Inference with Statistical Algorithm-Based Fault Tolerance. - Tong Xie; Jiawang Zhao; Zishen Wan; Zuodong Zhang; Yuan Wang 001; Runsheng Wang; Ru Huang 001; Meng Li 004 (CoRR, 2025)

A Variation-Tolerant Continuous-Time Ising Machine With eDRAM-Based Spin Interaction and Leaked Negative Feedback Annealing. - Zihan Wu 005; Jiahao Song; Xiyuan Tang; Bocheng Xu; Haoyang Luo; Youming Yang 002; Runsheng Wang; Xiaochen Bo; Yuan Wang 001 (IEEE J. Solid State Circuits, 2025)

UniPRE: An SNN-ANN Accelerator With Unified Max-Pooling Prediction and Redundancy Elimination. - Tao Zhang; Yi Zhong; Youming Yang 002; Zilin Wang; Zhaotong Zhang; Yuan Wang 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2025)

A Computing-in-Memory Engine Supporting One-Shot Floating-Point NN Inference and On-Device Fine-Tuning for Edge AI. - Haikang Diao; Haoyang Luo; Jiahao Song; Bocheng Xu; Runsheng Wang; Yuan Wang 001; Xiyuan Tang (IEEE J. Solid State Circuits, 2025)