A 1GHz Fractional-N PLL Clock Generator with Low-OSR ΔΣ Modulation and FIR-Embedded Noise Filtering. - Xueyi Yu; Yuanfeng Sun; Li Zhang 023; Woogeun Rhee; Zhihua Wang 001 (ISSCC, 2008)

A Hybrid Spur Compensation Technique for Finite-Modulo Fractional-N Phase-Locked Loops. - Li Zhang 023; Xueyi Yu; Yuanfeng Sun; Woogeun Rhee; Dawn Wang; Zhihua Wang 001; Hongyi Chen (IEEE J. Solid State Circuits, 2009)

A ΔΣ Fractional-N Synthesizer With Customized Noise Shaping for WCDMA/HSDPA Applications. - Xueyi Yu; Yuanfeng Sun; Woogeun Rhee; Hyung Ki Ahn; Byeong-Ha Park; Zhihua Wang 001 (IEEE J. Solid State Circuits, 2009)

An FIR-Embedded Noise Filtering Method for ΔΣ Fractional-N PLL Clock Generators. - Xueyi Yu; Yuanfeng Sun; Woogeun Rhee; Zhihua Wang 001 (IEEE J. Solid State Circuits, 2009)

Reconfigurable, fast AFC technique using code estimation and binary search algorithm for 0.2-6GHz software-defined radio frequency synthesis. - Jun Li 024; Ni Xu; Yuanfeng Sun; Woogeun Rhee; Zhihua Wang 001 (APCCAS, 2010)

A Continuously Tunable Hybrid LC-VCO PLL With Mixed-Mode Dual-Path Control and Bi-level Delta-Sigma Modulated Coarse Tuning. - Yuanfeng Sun; Jian Qiao; Xueyi Yu; Woogeun Rhee; Byeong-Ha Park; Zhihua Wang 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2011)