Optimizing Winograd Convolution on GPUs via Partial Kernel Fusion. - Gan Tong; Run Yan; Ling Yang 008; Mengqiao Lan; Jing Zhang; Yuanhu Cheng; Wentao Ma; Yashuai Lü; Sheng Ma; Libo Huang (NPC, 2022)

RV16: An Ultra-Low-Cost Embedded RISC-V Processor Core. - Yuanhu Cheng; Libo Huang; Yi-Jun Cui; Sheng Ma; Yongwen Wang; Bingcai Sui (J. Comput. Sci. Technol., 2022)

ImSPU: Implicit Sharing of Computation Resources Between Vector and Scalar Processing Units. - Hongbing Tan; Xiaowei He; Guichu Sun; Liquan Xiao; Yuanhu Cheng; Jing Zhang; Zhong Zheng; Quan Deng; Bingcai Sui; Yongwen Wang; Libo Huang (Euro-Par (2), 2024)

RVAM16: a low-cost multiple-ISA processor based on RISC-V and ARM Thumb. - Libo Huang; Jing Zhang; Ling Yang 008; Sheng Ma; Yongwen Wang; Yuanhu Cheng (Frontiers Comput. Sci., 2025)