An adaptive Non-Uniform Loop Tiling for DMA-based bulk data transfers on many-core processor. - Keni Qiu; Yuanhui Ni; Weigong Zhang; Jing Wang 055; Xiaoqiang Wu; Chun Jason Xue; Tao Li 006 (ICCD, 2016)

Queuing Theory-Guided Performance Evaluation for a Reconfigurable High-Speed Device Interconnected Bus. - Weiwen Chen; Keni Qiu; Jiqin Zhou; Yuanhui Ni; Yuanchao Xu 002 (TrustCom/BigDataSE/ICESS, 2017)

Pipeline Optimizations of Architecting STT-RAM as Registers in Rad-Hard Environment. - Zhiyao Gong; Keni Qiu; Weiwen Chen; Yuanhui Ni; Yuanchao Xu 002; Jianlei Yang 001 (TrustCom/BigDataSE/ICESS, 2017)

State-Transition-Aware Spilling Heuristic for MLC STT-RAM-Based Registers. - Yuanhui Ni; Zhiyao Gong; Weiwen Chen; Chengmo Yang; Keni Qiu (VLSI Design, 2017)

Power optimization through peripheral circuit reusing integrated with loop tiling for RRAM crossbar-based CNN. - Yuanhui Ni; Weiwen Chen; Wenjuan Cui; Yuanchun Zhou; Keni Qiu (DATE, 2018)

Low power driven loop tiling for RRAM crossbar-based CNN. - Yuanhui Ni; Keni Qiu; Weiwen Chen; Lixue Xia; Yu Wang 002 (SAC, 2018)

面向MLC STT-RAM的寄存器分配策略优化研究 (Optimization of Register Allocation Strategy for MLC STT-RAM). - Yuanhui Ni; Weiwen Chen; Lei Wang; Keni Qiu (计算机科学, 2018)

Redesigning pipeline when architecting STT-RAM as registers in rad-hard environment. - Zhiyao Gong; Keni Qiu; Weiwen Chen; Yuanhui Ni; Yuanchao Xu 002; Jianlei Yang 001 (Sustain. Comput. Informatics Syst., 2019)