A power efficient current-mode differential driver for FPGAs. - Yuanlong Xiao; Jian Wang 036; Jinmei Lai 001 (ASICON, 2015)

A universal automatic on-chip measurement of FPGA's internal setup and hold times. - Yuanlong Xiao; Jian Wang 036; Jinmei Lai 001 (IEICE Electron. Express, 2016)

Case for Fast FPGA Compilation Using Partial Reconfiguration. - Dongjoon Park; Yuanlong Xiao; Nevo Magnezi; André DeHon (FPL, 2018)

Transistor-Level Optimization Methodology for GRM FPGA Interconnect Circuits. - Zhengjie Li; Yuanlong Xiao; Yufan Zhang; Yunbing Pang; Jian Wang 036; Jinmei Lai 001 (FPGA, 2019)

An Automatic Transistor-Level Tool for GRM FPGA Interconnect Circuits Optimization. - Zhengjie Li; Yuanlong Xiao; Yufan Zhang; Yunbing Pang; Chengyu Hu; Jian Wang 036; Jinmei Lai 001 (ACM Great Lakes Symposium on VLSI, 2019)

Reducing FPGA Compile Time with Separate Compilation for FPGA Building Blocks. - Yuanlong Xiao; Dongjoon Park; Andrew Butt; Hans Giesen; Zhaoyang Han; Rui Ding; Nevo Magnezi; Raphael Rubin; André DeHon (FPT, 2019)

Fast Linking of Separately-Compiled FPGA Blocks without a NoC. - Yuanlong Xiao; Syed Tousif Ahmed; André DeHon (FPT, 2020)

HLS-Compatible, Embedded-Processor Stream Links. - Eric Micallef; Yuanlong Xiao; André DeHon (FCCM, 2021)

Meta-level issues in Offloading: Scoping, Composition, Development, and their Automation. - André DeHon; Hans Giesen; Nik Sultana; Yuanlong Xiao (CoRR, 2021)

PLD: fast FPGA compilation to make reconfigurable acceleration compatible with modern incremental refinement software development. - Yuanlong Xiao; Eric Micallef; Andrew Butt; Matthew Hofmann; Marc Alston; Matthew Goldsmith; Andrew Merczynski-Hait; André DeHon (ASPLOS, 2022)

HiPR: Fast, Incremental Custom Partial Reconfiguration for HLS Developers. - Yuanlong Xiao; André DeHon (FPGA, 2022)

HiPR: High-level Partial Reconfiguration for Fast Incremental FPGA Compilation. - Yuanlong Xiao; Aditya Hota; Dongjoon Park; André DeHon (FPL, 2022)

Fast and Flexible FPGA Development using Hierarchical Partial Reconfiguration. - Dongjoon Park; Yuanlong Xiao; André DeHon (FPT, 2022)

Asymmetry in Butterfly Fat Tree FPGA NoC. - Dongjoon Park; Zhijing Yao; Yuanlong Xiao; André DeHon (ICFPT, 2023)

RapidStream 2.0: Automated Parallel Implementation of Latency-Insensitive FPGA Designs Through Partial Reconfiguration. - Licheng Guo; Pongstorn Maidee; Yun Zhou; Chris Lavin; Eddie Hung; Wuxi Li; Jason Lau; Weikang Qiao; Yuze Chi; Linghao Song; Yuanlong Xiao; Alireza Kaviani; et al. (ACM Trans. Reconfigurable Technol. Syst., 2023)

RapidStream IR: Infrastructure for FPGA High-Level Physical Synthesis. - Jason Lau; Yuanlong Xiao; Yutong Xie 011; Yuze Chi; Linghao Song; Shaojie Xiang; Michael Lo; Zhiru Zhang; Jason Cong; Licheng Guo (ICCAD, 2024)

ExHiPR: Extended High-Level Partial Reconfiguration for Fast Incremental FPGA Compilation. - Yuanlong Xiao; Dongjoon Park; Zeyu Jason Niu; Aditya Hota; André DeHon (ACM Trans. Reconfigurable Technol. Syst., 2024)